Lowering the Error Floor of LDPC Codes Based on Bit-Rectification Strategy

Access Full Text

Lowering the Error Floor of LDPC Codes Based on Bit-Rectification Strategy

For access to this article, please select a purchase option:

Buy conference paper PDF
£12.50
(plus tax if applicable)
Add to cart
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)
Add to cart

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET 8th International Conference on Wireless, Mobile & Multimedia Networks — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

  • DOI:  10.1049/cp.2019.1150
  • ISBN: 978-1-83953-163-7
  • Location: Beijing, China
  • Conference date: 15-17 Nov. 2019
  • Format: PDF
This paper proposes a bit-rectification strategy to lower error floor of Low-density parity-check codes. Most erroneous bits are located by bit-searching algorithm and obtain more reliable message over parallel concatenated decoder. The negative effect of erroneous bits along with corresponding trapping sets will be avoided.

Inspec keywords: search problems; parity check codes; concatenated codes; decoding

Subjects: Optimisation techniques; Codes; Combinatorial mathematics

Related content

content/conferences/10.1049/cp.2019.1150
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading