Modeling the TTL-based mapping cache
Modeling the TTL-based mapping cache
- Author(s): Xiaogian Li ; Feng Qiu ; Hongbin Luo ; Hongke Zhang
- DOI: 10.1049/cp.2011.1424
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- Author(s): Xiaogian Li ; Feng Qiu ; Hongbin Luo ; Hongke Zhang Source: 2011 International Conference on Advanced Intelligence and Awareness Internet (AIAI 2011), 2011 p. 41 – 45
- Conference: 2011 International Conference on Advanced Intelligence and Awareness Internet (AIAI 2011)
- DOI: 10.1049/cp.2011.1424
- ISBN: 978-1-84919-471-6
- Location: Shenzhen, China
- Conference date: 28-30 Oct. 2011
- Format: PDF
In the Locator/ID separation network, the mapping cache in the border routes plays an important part to improve the network performance and the user experience. In this paper, we model the Time-To-Live (TTL)-based mapping cache to evaluate the cache hit rate. The analytical models get a formula of the cache hit rate as a function of the distribution of packet inter-arrival time and the value of TTL. In the mapping cache, the lifetime of a cache item is reset to TTL if it is fetched. The analytical models are based on a simple assumption that the sequence of inter-arrival time of packets can be modeled as independent, identically distributed (i.i.d.) random variables. The cache hit rate depends on the inter-packet time distribution and we derive the empirical distribution of inter-packet time from our campus network data. The accuracy of our models and the i.i.d. assumption is proved by comparing the results from the trace driven simulation, the renewal assumption with the empirical distribution obtained from the trace data, and using the renewal assumption with the analytical distribution. We also give the trace driven simulation results on the number of mapping items versus the change of the TTL to better understand the mapping cache behavior.
Inspec keywords: cache storage; IP networks
Subjects: Semiconductor storage; Computer networks and techniques; Memory circuits; Computer communications
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