A spatial hierarchy FPGA implementation with DPR square root partitions

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A spatial hierarchy FPGA implementation with DPR square root partitions

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  • DOI:  10.1049/cp.2011.0904
  • ISBN: 978-1-84919-505-8
  • Location: Shanghai, China
  • Conference date: 14-16 Nov. 2011
  • Format: PDF
The customized hardware platform for spatial hierarchy construction with DPR square root partitions is validly obtained. Specialized process structures and storage structures are constructed to ensure the reutilization of presorting results on each level. The objective functions for division evaluation oriented to specific applications are scheduled. DPR partitions are built to meet intensive square root finding requests. After optimizations for algorithm and architecture, such achievement provides the starting points for future development.

Inspec keywords: field programmable gate arrays; field effect memory circuits; circuit optimisation; integrated circuit modelling

Subjects: Logic and switching circuits; Semiconductor storage; Memory circuits; Logic circuits; Digital circuit design, modelling and testing

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