A FPGA ray tracing scheme with memory optimization facility
A FPGA ray tracing scheme with memory optimization facility
- Author(s): Huang Wei and Wan Wang Gen
- DOI: 10.1049/cp.2011.0903
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- Author(s): Huang Wei and Wan Wang Gen Source: IET International Communication Conference on Wireless Mobile and Computing (CCWMC 2011), 2011 p. 329 – 334
- Conference: IET International Communication Conference on Wireless Mobile and Computing (CCWMC 2011)
- DOI: 10.1049/cp.2011.0903
- ISBN: 978-1-84919-505-8
- Location: Shanghai, China
- Conference date: 14-16 Nov. 2011
- Format: PDF
This article presents a ray tracing acceleration system realized on FPGA platform. Additionally we make improvement to the memory accessing performance and achieve ideal ratio of performance against resources. Such work will gain ray tracing more applicable regions. The global scheme includes spatial indexing hierarchy module, ray generation module, pre-masking module, packet traversal module, arithmetic module and memory optimization facility which is described specially in this article..
Inspec keywords: integrated circuit modelling; circuit analysis computing; field effect memory circuits; circuit optimisation; field programmable gate arrays; ray tracing
Subjects: Electronic engineering computing; Semiconductor storage; Memory circuits; Graphics techniques; Computational geometry; Logic and switching circuits; Logic circuits; Digital circuit design, modelling and testing
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