This chapter discusses a watermarking-based hardware security methodology using an encrypted protein molecular biometric signature to secure hardware intellectual property (IP) cores against counterfeiting, IP piracy, and false assertion of IP ownership. In this method, the protein molecular biometric signature (watermark) is generated from the IP seller's protein sample using protein sequencing, followed by robust encryption using facial biometric signature-based encryption key. Subsequently, the obtained watermark (encrypted protein signature) is transformed into covert security constraints using the IP seller's mapping/embedding rule, which are then embedded into the design as an IP seller's digital evidence. Integration of the IP seller's authentic watermark provides a detective countermeasure against IP piracy and nullification of false assertion of IP ownership. The encrypted protein molecular watermarking methodology provides stronger digital evidence against piracy and greater resilience against tampering.

Ensuring security and trust within the global hardware design supply chain process is paramount. Intellectual property (IP) piracy and false IP ownership assertion are two primary threats that exist within the global design supply chain process. This chapter discusses a high-level synthesis (HLS)-based mathematical watermarking approach that exploits the characteristics of the design parameters and design space, viz. dispersion matrix and eigen decomposition framework, respectively. In this chapter, the IP seller is considered the defender and the system-on-chip (SoC) integration house is the attacker. The discussed mathematical watermarking methodology demonstrates a security framework that leverages the characteristics of the design space parameters chosen by the IP seller, as well as the design space's size in terms of resource configurations selected by the IP seller, to embed them as unique features for safeguarding the IP design. The discussed approach also employs AES encryption to generate encrypted watermarking constraints, which are further integrated/embedded into the hardware design (serving as digital evidence) and provide detective security countermeasures against potential intellectual property piracy and false IP ownership claim.

Designing reusable hardware intellectual property (IP) core (such as JPEG-CODEC) for multimedia/electronic systems involves managing competing design goals like latency and area during high-level synthesis (HLS). Additionally, it requires addressing the critical aspect of hardware security to prevent IP piracy and false IP ownership claim. This chapter discusses the generation of low-cost, secure IP design using the firefly algorithm (FA) based space exploration or design space exploration (DSE) and crypto-based watermarking (security) framework. The discussed crypto (key-driven) watermarking approach leads to the generation of watermarking constraints, which are further implanted into the hardware design through an HLS-based embedding process. This discussed low-cost security methodology facilitates IP piracy detection and resolution of false IP ownership assertion.

The chapter describes a high-level synthesis (HLS)-driven methodology for generating secure hardware intellectual property (IP) core design with fault detectability feature using multi-cut-based structural obfuscation and physical biometric (Chaurasia and Sengupta, 2023a). In this methodology, firstly, the IP design is leveraged with transient fault detectability feature and is transformed/obscured using multi-cut-based structural obfuscation. This transformation serves as the first layer of security, ensuring the protection of the design against potential reverse engineering attempts by an adversary. Subsequently, the design is covertly embedded with physical biometric of IP vendor. The embedded naturally unique biometric information of genuine IP vendor serves as the second layer of security, ensuring the protection of the design against IP piracy. Thus, HLS-driven hardware security methodology can concurrently offer security of "fault-detectable IP designs" against the following hardware threats: (a) potential reverse engineering threat by an adversary from the SoC layout stage in an untrustworthy foundry and (b) IP piracy by an adversary that may present in the SoC integration house.

The rest of the chapter is structured as follows: Section 8.1 provides the introduction of the chapter; Section 8.2 delves into the various threat model scenario; Section 8.3 provides background on transient fault; Section 8.4 explores the multi-cut-based structural obfuscation technique and physical biometrics for enhanced hardware IP security; Section 8.5 presents a case study on IIR filter application framework; Section 8.6 presents security features of the methodology; Section 8.7 analyzes the security of IP design achieved through multi-cut based structural obfuscation and physical biometrics; Section 8.8 concludes the chapter by summarizing its findings and implications.

The chapter describes the fundamentals of high-level synthesis (HLS)-based hardware Trojan and its various types. This chapter provides an overview of hardware Trojan and discusses the motivation for an adversary to perform an HLS-based hardware Trojan attack. Further, it highlights the potential sites for hardware Trojan insertion in the semiconductor design supply chain. It discusses in detail the three different types of HLS-based hardware Trojan attacks followed by hardware Trojan in 3PIP modules.

The organization of the chapter is as follows: Section 10.1 discusses a brief overview of hardware Trojan, different ways of the hardware Trojan insertion followed by the Trojan insertion during HLS and its potential effects; Section 10.2 provides an overview of three different types of HLS-based hardware Trojan attacks, viz. battery exhaustion, degradation, and downgrade, and discusses the threat scenario. Section 10.3 presents insights on battery exhaustion attacks with a motivational example. Section 10.4 presents insights on degradation attacks with a motivational example while discussing its impact on security and overhead. Section 10.4 presents insights on downgrade attack and explains with the help of compromising secure hash algorithm; Section 10.5 presents insights on hardware Trojan in 3PIP modules and explains using an example; Section 10.6 concludes the chapter.

Research on HLS has been ongoing for the last two decades by the scientific community. However, HLS exploited for security, has become the focus in recent years. It has been an active area of interest for the security community all over the globe, especially in the last few years due to manifold benefits offered by HLS such as lower overhead, flexibility in architecture exploration, and design automation. Security and trust in hardware have become more important than ever before due to the emergence of several points of vulnerabilities and the growing sophistication of cyber-attacks.

Through this book, a reader gained valuable insights on how efficiently the HLS framework can be leveraged to offer several benefits for hardware security. This is particularly important when designing specialized hardware (or IPs/modules) for data-intensive/power-hungry applications such as convolutional layer in CNN, signal filtering through digital filters, image processing through image processing filters, multimedia compression/decompression using JPEG CODECs, as well as other digital signal processing applications, etc. The hardware IPs of such algorithms/applications are typically designed using HLS instead of starting from RTL (or lower levels) due to the complexity involved. Therefore, it is natural, that the security of such hardware IPs should be dealt with by exploiting the HLS framework such that it results in lower overhead, lesser design time, and greater flexibility for the designer. Hardware security of smaller applications with lesser complexity such as traditional combinational/sequential circuit blocks can be handled at the RTL or gate level. However, it's not pragmatic to do so for the aforementioned complex applications.

This book, therefore, provided an important guide for readers to understand how to design secure specialized hardware IPs using HLS. The book covers how HLS flow can be used to address critical security threats (that can potentially affect reusable hardware IPs) such as IP piracy, IP ownership abuse, watermark collision, ghost insertion search attack, tampering attack, forgery attack, reverse engineering, malicious RTL alteration, SCA, etc.