The chapter gives an introduction on security requirements of co-processors for machine learning (ML) and digital signal processing (DSP) applications and the role of biometrics in securing them. This introduction of the book tries to build interest in readers about the various DSP and ML co-processors; behavioral synthesis design process for generating secured DSP and ML co-processors and importance of biometric security for hardware authentication.

The chapter is organized as follows: Section 1.1 introduces about the co-processors, different hardware threats, and conventional security solutions; Section 1.2 highlights the significance of behavioral synthesis in designing and securing co-processors; Section 1.3 introduces about the co-processors for ML applications, why ML co-processors need to be secured, and how behavioral synthesis plays a crucial role in securing ML co-processors; Section 1.4 introduces about the behavioral synthesis perspective in designing and securing DSP co-processors; Section 1.5 introduces about the biometric security based on fingerprint, face, and palmprint for ML and DSP co-processors.

The chapter describes a robust physiological biometrics-based methodology using facial signature biometric for hardware security and intellectual property (IP) core protection (Sengupta and Rathor, 2021). In this methodology, first, the facial biometric signature of IP vendor is extracted and subsequently transformed into encoded constraints for hardware security using multi-level encoding specified by IP vendor. Next, these generated secret constraints for hardware security are inserted inside the design at the register allocation stage of high-level synthesis (HLS) process. These embedded facial security constraints act as digital evidence to enable security of IP core design against several security threats. The hardware security methodology based on facial biometric enables the robust and seamless detective control against the threat of IP piracy. Additionally, it also protects the ownership rights of authentic IP vendor, in case if a rogue system on chip (SoC) integrator or an adversary at foundry, falsely claims the IP ownership.

The rest of the chapter has been organized as follows: Section 3.1 provides the introduction of the chapter; Section 3.2 highlights the importance of HLS for designing digital signal processing (DSP) coprocessors; Section 3.3 presents the discussion and analysis of alternative techniques used for Intellectual property protection (IPP) of DSP coprocessors; Section 3.4 explains the features of facial biometric for IPP and its advantage over fingerprint biometrics; Section 3.5 shows the summary of facial biometric methodology for IPP; Section 3.6 explains the details of facial biometric methodology for IPP; Section 3.7 presents a case study of designing safeguarding N-point discrete Fourier transform (DFT) design using facial biometrics; Section 3.8 discusses security properties of facial biometric methodology for hardware security; Section 3.9 provides analysis and discussion and Section 3.10 concludes the chapter.

The chapter describes the applications of biometric-based hardware security methodologies to provide symmetric protection of ownership rights for intellectual property (IP) buyer and seller. Additionally, it also presents the application of facial biometric-based hardware security for protecting Trojan-secured DSP designs against IP piracy (Chaurasia and Sengupta, 2022a, 2022b). To provide symmetric security for IP buyer and seller, first, the fingerprint biometric of IP buyer in the form of secret hardware security constraints is embedded into the digital signal processing (DSP) design during high-level synthesis (HLS). This embedded fingerprint signature IP buyer safeguards his/her rights against an adversary or an untrustworthy IP seller. Subsequently, post obtaining the IP buyer fingerprint embedded design, the facial biometric of IP seller is inserted into the design. Thus, the embedded security constraints (digital evidence) corresponding to fingerprint biometric and facial biometric signature of IP buyer and seller, respectively, enables the symmetric protection of their ownership rights. Additionally, in case of piracy, the embedded facial biometric signature also enables the robust and seamless detective control against pirated versions. Further, for protecting the Trojan-secured designs against IP piracy, first the Trojan-secured scheduled design is generated. Subsequently, the facial security constraints are inserted into the Trojan-secured design using HLS. These embedded facial security constraints enable the piracy detection control for Trojan-secured DSP designs as well. Thus, isolating pirated versions before integrating into system on chip (SoC) systems.

The organization of the chapter is as follows: Section 5.1 discusses about the introduction of the chapter; Section 5.2 presents the discussion on contemporary approaches for symmetrical IP core protection; Section 5.3 explains the process of HLS-based symmetrical IP core protection using IP seller facial biometric and IP buyer fingerprint biometric; Section 5.4 shows the protection of IP seller right's against the false claim of IP ownership; Section 5.5 shows the protection of IP buyer right's using fingerprint biometric signature; Section 5.6 explains the piracy detection process; Section 5.7 presents the process of employing facial biometric for protecting Trojan-secured IP cores against piracy; Section 5.8 discusses and analyses the security and design cost of symmetrical IP core protection technique and for, protecting Trojan-secured designs against piracy; Section 5.9 concludes the chapter.

Reusable intellectual property (IP) cores are widely used in all modern digital integrated circuits (ICs) in the form of application-specific processors or hardware accelerators. Reusable IP cores integrated in system-on-chip (SoC) platforms of integrated circuits and systems provide a powerful blend of yielding superior design productivity with reduced design cycle time. However, leveraging advantages of IP core require low-cost security against threats such as piracy and fraudulent claim of ownership. This chapter discusses the following aspects: (a) security-aware end-to-end high-level synthesis (HLS)-based design methodology using low-cost steganography technique for protecting IP cores used in digital ICs; (b) security-aware end-to-end HLS-based design methodology using low-cost biometric signature for protecting IP cores used in digital ICs; (c) secured RTL designs of reusable IP core embedding secret steganography mark and biometric signature respectively offering low overhead, strong robustness, and greater security in terms of lower probability of coincidence and higher tamper tolerance. Further, the chapter also discusses the achieved robustness of > 2× (i.e., stronger digital evidence as evident from the lower probability of coincidence) and lower design cost (~6.17%) than state-of-the-art approaches.

In the modern electronic era, the increased usability and acceptability of reusable intellectual property (IP) cores induce the necessity to secure them from various hardware security threats and attacks. This chapter presents a taxonomy of hardware security methodologies for IP cores and a detailed design flow of hardware integrated circuits (ICs) along with vulnerability points where potential attacks/threats are possible. Trustworthy and untrustworthy regimes in the design flow have also been highlighted in the discussion. Further, a discussion of detective and preventive control-based hardware security approaches used for hardware IP cores have also been presented, including an analysis of prominent structural obfuscation, logic locking (logic encryption), and IP core protection (IPP) techniques. Each approach has been lucidly explained in terms of its threat model, algorithm, and security analysis. Finally, a security comparison of hardware IP obfuscation approaches in terms of strength of obfuscation security metric as well as security comparison of IPP approaches in terms of probability of coincidence security metric have also been introduced.