Written by an acknowledged expert in the field, this book focuses on approaches for designing secure hardware accelerators for digital signal processing and image processing, which are also optimised for performance and efficiency. State-of-the art security and optimization algorithms are presented, and their roles in the design of secured hardware accelerators for DSP, multimedia and image processing applications are explored. The book begins with an introduction to the principles of secured and optimized hardware accelerators for DSP and image processing applications. The following topics are then given thorough and systematic coverage: cryptography driven IP steganography for DSP hardware accelerators; double line of defence to secure JPEG codec hardware for medical imaging systems; integrating multi-key based structural obfuscation and low-level watermarking for double line of defence of DSP hardware accelerators; multimodal hardware accelerators for image processing filters; fingerprint biometric for securing hardware accelerators; keytriggered hash-chaining based encoded hardware steganography for Securing DSP hardware accelerators; designing N-point DFT hardware accelerator using obfuscation and steganography; and structural transformation and obfuscation frameworks for data-intensive IPs. Intended primarily for researchers and practicing engineers, the book will also be of interest to graduate students with a particular interest in hardware device security.
Inspec keywords: watermarking; cryptography; digital signal processing chips; codecs; steganography; multimedia computing; image processing
Other keywords: image processing hardware accelerators; fingerprint biometric; DSP; multimodal hardware accelerators; cryptography-driven IP steganography; key-triggered hash-chaining-based encoded hardware steganography; multimedia hardware accelerators; JPEG codec hardware; secured hardware accelerator design; image processing filters; optimized hardware accelerators; medical imaging systems; low-level watermarking; multikey-based structural obfuscation
Subjects: Multimedia; Microprocessor chips; Microprocessors and microcomputers; Signal processing and detection; Digital signal processing; General and management topics; General electrical engineering topics; Optical, image and video signal processing; Digital signal processing chips; Digital signal processing chips; Security aspects of hardware
This chapter provides a background introduction on hardware accelerators, followed by its relevance in today's digital world as well as the security modules/ algorithms being used to secure a hardware accelerator and finally ending with the paradigm shift needed for the future. The chapter is organized as follows: Section 1.1 discusses about the definition, significance and application of hardware accelerators, followed by the role of electronic system level (ESL) synthesis in hardware accelerator design in Section 1.2; Section 1.3 provides significant details on the popular hardware accelerators for digital signal processing (DSP) and image processing applications by including details of its mathematical function/algorithm. Section 1.4 presents a background summary of important security algorithm/modules used for securing hardware accelerators by especially giving reference to the chapters where it is discussed; Section 1.5 explains the new paradigm shift expected in future for hardware and very large scale integration (VLSI) communities; Section 1.6 concludes the chapter, while Section 1.7 provides questions and exercise for the readers.
The chapter describes a cryptography-driven intellectual property (IP) steganography process for securing hardware accelerators. The chapter focusses on hardware accelerators that are used popularly in digital signal processing (DSP) applications for modern electronics systems/products. A detailed elaboration on the salient features of cryptography-driven IP steganography process, its differences from DSP watermarking approaches, other hardware steganography approaches, details of secret steganography constraint generation process, embedding process, detection process and details on case studies have been provided. The chapter is organized as follows: Section 2.1 discusses the background of this topic; Section 2.2 presents the contemporary approaches for securing hardware accelerators. Section 2.3 presents the crypto-based steganography process for securing hardware accelerators; Section 2.4 introduces a new crypto-stego tool for securing hardware accelerators; Section 2.5 presents the case studies on DSP hardware accelerators; Section 2.6 concludes the chapter; Section 2.7 provides some exercise for the readers.
The chapter describes a double line of defence mechanism for securing a JPEG codec hardware accelerator used in medical imaging systems. The chapter starts with the background/motivation of JPEG codec for imaging modalities, followed by discussing the dual line of security based on structural obfuscation and crypto-steganography for the image compression hardware, and highlighting the results on case studies in terms of security and overhead. The chapter is organized as follows: Section 3.1 introduces the chapter; Section 3.2 discusses on the motivation of using JPEG compression in medical imaging systems; Section 3.3 presents the salient features of the chapter; Sections 3.4 and 3.5 explain the process of double line of defence for a JPEG codec hardware accelerator; Section 3.6 presents the analysis on case studies; Section 3.7 concludes the chapter; Section 3.8 presents some exercise for readers.
The chapter describes a double line of defence mechanism for securing hardware accelerators using key-based structural obfuscation (SO) and physical-level watermarking. The presented approach discussed in this chapter is capable of securing against combined threat models of reverse engineering (leading to Trojan insertion) and intellectual property (IP) piracy as preventive and detective control.
The chapter describes hardware accelerators for image processing filters, including design methodology and security technique employed for the following: blur filter, sharpening filter, embossment filter and Laplace edge-detection (ED) filter. The chapter is organized as follows: Section 5.1 discusses the reasons for using dedicated image processing filter hardware, Section 5.2 discusses the motivation for designing secure image processing filter hardware accelerators, Section 5.3 presents the salient features of this chapter, Section 5.4 discusses some selected contemporary approaches, Section 5.5 discusses the theory of 3 × 3 filter hardware accelerator, Section 5.6 presents designing of functionally reconfigurable obfuscated 3 × 3 filter hardware accelerator, Section 5.7 discusses the theory of 5 × 5 filter hardware accelerator, Section 5.8 presents designing of obfuscated 5 × 5 filter hardware accelerator, Section 5.9 presents designing of secured application specific filter hardware accelerators, Section 5.10 presents the equivalent MATLAB® codes for image processing filters, Section 5.11 presents additional information on image processing convolution filters, Section 5.12 presents analysis of case studies, Section 5.13 concludes the chapter and Section 5.14 presents some questions and exercise for the readers.
The chapter describes a promising approach for securing hardware accelerators against intellectual property (IP) piracy and fraud IP ownership threat using biometric fingerprinting. Securing a hardware IP using biometric fingerprint is a paradigm shift from the contemporary approaches. This chapter lucidly explains the biometric-fingerprint-based process using real-life digital signal processing (DSP)/image processing application. The chapter is organized as follows: Section 6.1 discusses about the introduction of the chapter; Section 6.2 highlights the salient features of this chapter; Section 6.3 presents discussion on some contemporary approaches; Section 6.4 explains the threat model where biometric-fingerprint-based security approach is useful; Section 6.5 provides a high-level perspective of biometric fingerprint approach for securing hardware accelerators; Section 6.6 presents the details of biometric-fingerprinting-based IP protection approach; Section 6.7 presents analysis on case studies; Section 6.8 discusses the advantages of this approach and Section 6.9 concludes the chapter.
This chapter describes a multi-encoding-driven key-triggered hash-chaining-based hardware steganography approach for securing digital signal processing (DSP) hardware accelerators which uses multiple layers of encoding and key-based parallel switch blocks (SBs) to drive multiple secure hash-chaining blocks in the algorithm. The presented approach is highly robust against fraud ownership claim and piracy threats. The chapter is organized as follows: Section 7.1 provides some introduction to the research problem, followed by some discussion on other selected approaches in Section 7.2; Section 7.3 describes the presented hash-chaining-based hardware steganography approach. Section 7.4 presents the design process of securing finite impulse response (FIR) filter using this hardware steganography process; Section 7.5 presents the KHC-stego tool of this corresponding key-triggered hash-chaining hardware steganography approach; Section 7.6 discusses the analysis on case studies; Section 7.7 concludes the chapter, while Section 7.8 presents some exercise for readers.
N -Point DFT is an important DSP algorithm which fmds numerous applications in electronics. A hardware accelerator design of DFT is vital to improve system performance. However, the design process of a DFT hardware accelerator poses security risks due to growing hardware threats such as Trojan insertion, false claim of ownership and piracy. This entails enabling security of DFT hardware accelerator designs, by the designer/vendor. This chapter discusses a secured design flow of N -point DFT hardware accelerator using HLS framework. The robust security of DFT hardware accelerator design has been ensured using two security mechanisms, structural obfuscation and crypto-steganography. Steganographybased security mechanism employed on the top of structural obfuscation enables detective control along with preventive control. The case study of 4 -point DFT hardware accelerator in terms of security and design cost analysis shows that robust security has been achieved at the cost of negligible design overhead.
The chapter describes a structural transformation-based obfuscation approach using pseudo-operation mixing for securing data-intensive cores or hardware accelerators. The presented approach is based on pseudo-operation mixing algorithm that attains significant structural obscurity in the design to enable unobviousness without affecting the correct functionality. The chapter is organized as follows: Section 9.1 discusses about the introduction of the chapter; Section 9.2 describes the structural transformation-based obfuscation methodology; Section 9.3 presents pseudo operation mixing based structural obfuscation (POM-SO) tool that is capable of performing pseudooperation mixing-based structural obfuscation (SOB); Section 9.4 presents analysis of case studies in terms of security and design cost, especially focusing on digital signal processing (DSP) hardware accelerators; Section 9.5 presents conclusion; Section 9.6 provides some exercise and questions for readers.
