In this chapter, many aspects of III-V semiconductor transistors were reviewed. The following topics was discussed: epitaxial growth techniques; heterostructure and quantum well; heterojunction bipolar transistors; high electron mobility transistors; quantum well MOSFETs; and nanowire field effect transistors.

In power-constrained very large scale integration (VLSI) design, the transistors need to operate with extremely scaled supply voltage ( 0.4-0.5 V) and must have good electrostatic integrity to minimize the static power dissipation. But these lead to compromise in switching speed. This competing requirement necessitates the introduction of new material to form the channel of a MOS transistor, in which the inversion charge carriers travel with much higher velocity than that in silicon. With this, the loss of switching speed can be reduced. III-V compound semiconductors such as GaAs, InGaAs and InAs have very good electron transport properties. The mobility of electrons in InGaAs or InAs is more than ten times higher than that for silicon at a comparable sheet charge density [1]. However, one intrinsic drawback of the MOS transistor made of III-V semiconductors is worse device electrostatic integrity. Therefore, ultrathin body (UTB) structures like UTB-on-insulator (UTBOI) structure, FinFET or trigate structure and nanowire field effect transistor (FET) structure with III-V-based channel material have gained attention of the semiconductor device researchers for applications in next generation VLSI circuits. It may be noted that any new technology is desired to be compatible with an Si-based CMOS platform for cost-effective mass production and system-on-chip applications. Direct wafer bonding (DWB) technique is an important approach to grow III-V-OI structures with thin buried oxide (BOX) layers on Si wafers. This chapter provides a comprehensive overview of a UTB III-V-OI-Si MOS transistor. The advantages of using III-V channel materials over Si are summarized using calibrated technology computer-aided design (TCAD) simulation results. Gate-source/drain (G-S/D) underlap technique is discussed as an approach to enhance electrostatic integrity. Finally, UTB, GaAs-OI structure is briefly introduced as a candidate for a p-channel MOS transistor.

In this chapter, we report p⁺-n⁺-i-n⁺ (n -type) and n⁺-p⁺-i-p⁺ (p -type) SiGe/Si hetero double gate tunnel field-effect transistor (TFET) (H-DGTFET) for low power circuit applications. To achieve the optimum performance of the above devices, the Silicon (Si) and Germanium (Ge) composition of 30% and 70% (SiO₃ Ge_0.7), respectively, considered in source region, and a heavily doped (HD) layer placed in the channel near the source-channel junction are employed. Due to lower tunnel resistance offered by SiGe, the technology computer aided design (TCAD) device simulations of both the configurations show superior results in terms of DC and analog/radio frequency (RF) parameters as compared to the conventional TFETs. However, linearity of n-type device is analyzed in terms of VIP2, VIP3, and PldB. Furthermore, the circuit-level performance assessment is done by implementing complementary primary digital circuits (such as an inverter, NAND, and NOR logics) using lookup table-based Verilog-A model of the H-DGTFET. Comparison table shows impressive results in terms of digital performance parameters such as static noise margin (SNM), noise margin high (NM_H ), noise margin low (NM_L ), high-to -low delay (τ_phl ), low-to-high delay (τ_phl,), and propagation delay (τ_p) as compared to the recently reported work

In this chapter, we will look into some of the reliability concern in first few sections and fi nally propose a simulation (numerical) framework along with model development to understand these effects.

The relentless advances in the complementary metal oxide semiconductor (CMOS) technology have mainly enabled through dimensional downscaling of the transistor which brings out numerous challenges such as controlling short channel effects (SCEs), leakage current and fabrication complexity of forming high-quality metallurgical junction at sub-nanoscale regime. Junctionless (JL) concept in the transistor has emerged recently and shown tremendous potential for the future technology generation. It not only simplified the fabrication process but also provided the comparable performance to those of conventional junction-based metal oxide semiconductor (MOS) devices. This work, for the first time, demonstrates the impact of oxide thickness variation (OTV) on a 14 nm junctionless FinFET (JL FinFET) using extensive technology computer-aided design (TCAD) device simulation. Results show that the deviation in threshold voltage and OFF-current are seriously impacted by OTV for JL FinFET structure as compared to the normal inversion mode (IM) counterparts. Furthermore, the joint impact of all the intrinsic statistical variability sources including OTV, random dopant fluctuation (RDF) and gate work function variation (WFV) on threshold voltage has been investigated.

In modern SOC design SRAM has become an integral part owing to its capability to form a bridge and overcome the speed mismatch problem between the high speed processor and the low speed data storage devices. Because of the read and write operation of SRAM cell having conflicting transistor sizing requirement, it is very difficult to maintain the transistor size to satisfy both the needs. The destructive nature of read operation enforces a serious thought about SRAM cell data stability. Transistor sizing and cell stability already being a critical problem becomes even more critical when we consider the process and temperature variation. Thus the SRAM should be designed with keeping the process and temperature variation in mind. The random fluctuation in device parameters such as transistor width, length, oxide thickness, oxide capacitance and doping concentration leads to variation in the threshold voltage and other transistor characteristics. The change in these transistor characteristics alters the SRAM cell performance. Hence this should also be taken care of to ensure the cell performance to be in the desired range even in presence of random fluctuation during fabrication process. The various performance measure such as SNM, write SNM, speed and power consumption must be tested under worst process corner as well over a wide temperature range to ensure that they lie in the acceptable range during worst operating condition. Also these parameters must be tested using Monte Carlo simulation to ensure a robust operation in presence of random fluctuation during fabrication process.

This chapter discusses the various methods of electrical modelling of CNT- and GNR-based nano-interconnects. It also presents the ABCD parameter matrix-based method for the modelling of performance and signal integrity effects in CNT- and GNR-based VLSI nano-interconnects. The developed methodology is proven to be almost 100% accurate as SPICE with huge reduction in the computational burden. It is pointed out that both CNTs and GNRs have tremendous potential in becoming the next generation VLSI interconnects.

In this chapter a holistic approach towards the design of energy-efficient circuitry has been discussed. The novel material graphene with extraordinary mechanical, electrical, thermal and magnetic properties has been shown to have a huge potential in replacing copper for clocking the nanomagnetic-based circuits so that the huge current required for generating external magnetic field can be reduced. Through simulation results the above mentioned has also been established. This chapter on the other hand also provides an insight on nanomagnetic computing for next generation interconnects and logic design. The role of MQCA-based digital arithmetic circuits and their impact has also been well demonstrated in this chapter.

In today's sophisticated nanoera and miniaturised densely packed integrated circuit (IC) designs, on-chip interconnects have become one of the dominant governing factors in determining the overall performance of very large scale integration (VLSI) system. In pursuit to attain high performance, to quench the thirst of continuously increasing demands of semiconductor VLSI industry and to boost up the integrated applications on the calculated limited silicon chip area, hunt for new potential and prospective design techniques have always been on priority and rigorously explored by several researchers. Current mode approach for on-chip interconnects is one of the aptly suited signalling schemes and effective performance improvement techniques for high-end IC designs. An accurate analytical model formulation of on-chip interconnects together with prospective current mode signalling (CMS) scheme and evaluating their performance are crucial and important issue. In this chapter, explicit expressions of various performance metrics for on-chip interconnects are formulated. The performance of interconnects using two varying signalling schemes namely conventional voltage and advanced current mode is investigated. The various performance metrics considered are voltage swing over interconnect line, delay, power dissipation, energy dissipation and bandwidth. It is found that voltage mode signalling (VMS) has advantage of reduced power and energy dissipation of nearly 8.6% and 9.2%, respectively, as compared to CMS scheme. It is also investigated that CMS has about 53% lesser delay and 161% higher bandwidth than VMS scheme. The effect of interconnect length and pulse period variations on the performance parameters of the interconnect using VMS and CMS schemes are also analysed. The proposed analytical model results are validated using SPICE simulation EDA tool and high level of accuracy has been realised. The present work keenly focuses on advanced current mode approach and henceforth analysing the effectiveness of different signalling schemes for high performance on-chip VLSI interconnects in ICs.

This chapter discusses the design aspects of TSVs for 3D -IC applications. To improve the performance of TSVs, different insulating liners with low dielectric constants are used in place of the conventional insulating liner. Moreover, it has been noticed that the TSVs with copper filler material faces many problems such as skin effect, high resistance and electromigration effects. In order to overcome these problems and to improve the signal integrity, multiwalled carbon nanotubes (MWCNTs) are used that further improves the performance of TSVs. All the proposed structures are designed using the industry standard HSPICE simulator. The performance improvements in the proposed structures are verified by comparing the results with the conventional TSVs.

The package of the silicon chip is an important aspect of VLSI. The package determines the size of ICs. Different IC packages allow the dies to connect with the PCB and it affects the performance of IC. These packages offer a connection with PCB, atmosphere protection and mechanical stability for the IC. The demand of improvement in IC package is increasing day by day due to the increased density of IC. The design of packages grew from through-hole to surface mount technology, from WB to flip -chip and from dual-inline packaging to chip scale packaging. Although there has been tremendous progress in this area, it is in the middle of another evolution. This progress is the evaluation of the 3D packaging design. This design provides more than 100% PE and enhances performance metrics through decreased interconnection length. This is achieved by vertical connections of stacking chips using TSVs. Vertically connected TSVs also facilitate heterogeneous integration of dies in realising on a single chip. However, the selection of filler material in TSVs plays a vital role in the reliability of 3D ICs. There are some challenges in the areas of thermal management and electrical design. In the present study, four different surrounding materials, that is, SiO₂ , Si₃N₄ , Al₂0₃ and Hf0 ₂ have been considered. The equivalent stress and the resultant structure deformation of filler material (Cu and CNT) of TSVs are observed. It is noticed that the deformation in the structure of CNT-based TSVs is lesser as compared to Cu -based TSVs. Further, Hf0 2 possesses significantly lesser deformation as compared to SiO₂ and Al₂O₃.

As the transistor size scales down exponentially to nanometric dimensions, the susceptibility of electronic circuits to radiation increases drastically. Protection against the radiation is important in the field of biomedical, aerospace, communication and computing. Flip-flops (FFs) and static random access memories (SRAMs) are used to store the data in many critical applications where their performance must be resilient to radiation exposures to guarantee reliability. Therefore development of resilient FFs and SRAM are the challenging and demanding problems. In this chapter, different approaches are analysed to design these radiation hard circuits.

Phase change memory (PCM) functions by thermally induced phase change of chalcogenide material, typically from disordered highly resistive amorphous phase with short range atomic order and low free electron density, to a low resistance crystalline phase with long range atomic order and high free electron density, or vice versa [1,2]. PCM is one of the potential emerging nonvolatile memory (NVM) technologies to replace flash memory and be the technology for storage class memory due to its desirable properties such as short access time, long data retention, high endurance, scalability, CMOS compatibility and multibit storage [3-8]. Hence it is time to have an accurate electrical model of the PCM in order to realise a straightforward and timely implementation of PCM in an integrated circuit. This chapter presents the electrical circuit model of multibit PCM cell that accurately simulates the temperature profile, the crystalline fraction and the resistance of the cell as a function of the programming pulse. Also, the precise modelling of the drift phenomenon of resistance and threshold voltage at the amorphous phase is presented. The presented model's I-V characteristics are correlated with experimental data to demonstrate the validity of the developed PCM model. Next this chapter presents the analysis of PCM cells on a nanocrossbar as a memory system. The effect of connecting wires resistance in the performance of the PCM array structure, the amount of energy lost across each PCM cell and programmed state of the PCM cell is also discussed. It has been shown that the energy consumed in connecting wires decreases the power supplied to PCM cells thus resulting in higher programmed low resistive state (Rcrystalline). Additionally, methods to mitigate the programmedRcrystalline reliability issue are discussed in detail. Finally, the chapter concludes with the discussion on PCM-based memory application in implementing a logic function using the look-up-table (LUT), that is, PCM-based LUTs.

This chapter contains various designs of ternary logic gates and adders using complementary metal oxide semiconductor transistors (CMOS) and carbon nanotube field effect transistors (CNTFETs). As the time goes by binary logic is getting harder to implement on smaller scale, so ternary logic becomes a better alternative of the same. Ternary logic has the simplicity over binary logic and it is energy efficient also. In today's world when it's a challenge to implement the circuit design on as small level as possible, binary logic is limited due to large number of interconnects and large chip area, which is reduced in ternary logic. In ternary logic, there is a requirement of the multithreshold transistors, which can switch on and switch off on the particular voltage level when the circuit demands, since CNTFET's threshold can be changed by varying their chirality or tube diameter they have become the most suitable devices to implement ternary logic. In this chapter various research works on ternary gates and adders will be discussed and a comparison between them will be made on various performance parameters such as power delay product (PDP), transistor count and time delay. These parameters are evaluated and compared by simulating these circuits.

Square/triangular wave generators are very important building blocks and find wide applications in resistive/capacitive sensor interfaces, pulse width modulation (PWM), analogue to digital convertor and so on. A variety of generator circuits have been reported in the literature so far. This chapter gives a brief review of existing generator circuits. To further enrich the area, this chapter proposes a novel square/triangular wave generator circuit, which is realised using single extra-X second generation current conveyor (EXCCII), four resistors and one grounded capacitor. The circuit provides both square wave and triangular wave in voltage-mode simultaneously. The circuit can operate at the frequency as low as 100 mHz and is capable of providing a wide sweep range of frequency of six decades (100 mHz to 310 kHz). The proposed generator can precisely detect the capacitor variations up to six decades in the range of 100 pF to 100 mF. Therefore, the proposed circuit finds suitable application as capacitive sensor interface with low-voltage and low-power characteristics. The effects of nonidealities and parasitic of EXCCII along with the effects of temperature variations on the proposed generator circuit are studied. The possible aspect of adjusting the duty cycle of output waveforms via DC current source is also shown. The theoretical proposal has been verified by SPICE simulations.

In this chapter we have provided a detailed description to TFs, its origin and its impact on integrated circuits. Further, we have discussed recent state-of-the-art methodologies present in the literature that provides security and/or tolerance subsequent CS doesn't require shifting of primary outputs. Hence, overall schedule delay is not affected. Similarly, as shown in Figure 16.15, for k = 10 and k m = 4, a small increment in the delay for [4] in case of large size benchmarks is observed. However, the delay overhead is within acceptable limits. (Note: during above delay comparison the delay overhead of two CS due to comparators and voter is not considered for analysis of delay overhead. This was done to provide analysis of delay overhead resulting only due to shifting of operations during scheduling and allocation.)