This book presents advanced forensic detective control and obfuscation techniques for securing hardware IP cores by exploring beyond conventional technologies. The theme is important to researchers in various areas of specialization, because it encompasses the overlapping topics of EDA-CAD, hardware design security, VLSI design, IP core protection, optimization using evolutionary computing, system-on-chip design and finally application specific processor/hardware accelerator design for consumer electronics applications. The book begins by introducing forensic detective control and obfuscation mechanisms for hardware and IP core security. Further chapters cover hardware stenography, digital signature driven hardware authentication, fault-secured IP cores using digital signature-based watermarks, multi-level watermarking, cryptosystem-based multi-variable fingerprinting, multi-phase and hologram-based obfuscation, and security of functionally obfuscated DSP cores.
Inspec keywords: watermarking; digital signal processing chips; steganography; cryptography; industrial property
Other keywords: cryptosystems; functional obfuscation; forensic detective control; vendors rights; IP core protection; intelectual property core security; hardware steganography; fault-secured DSP circuits; DSP; digital signal processing; hologram-based obfuscation; consumer technology; watermarking; buyers rights
Subjects: Digital signal processing chips; Security aspects of hardware; Digital signal processing chips; Cryptography
This chapter introduces the reader to the concepts of hardware security as well as exposing them to the new frontiers on hardware (intellectual property (IP) core) security from the perspective of forensic detective control mechanisms and obfuscation techniques. The book explicitly emphasizes the emerging solutions in the literature on hardware security of digital signal processing (DSP) cores. This has not been covered in any book so far. The reader is expected to have some foundational knowledge of very-large scale integration (VLSI), digital hardware design flow, high-level synthesis (HLS) and optimization. The readers can use IP Core Protection and Hardware-Assisted Security for Consumer Electronics to gain some pre-knowledge in the field.
This chapter discusses forensic detective control using hardware steganography for intellectual property (IP) cores or integrated circuits. The chapter is organized as follows: Section 2.1 introduces the utility or applications of hardware steganography; Section 2.2 discusses the threat model for which hardware steganography is applicable; Section 2.3 presents comparative study on contemporary approaches; Section 2.4 explains the IP core steganography model; Section 2.5 discusses forensic detective control using hardware steganography for digital signal processing (DSP) cores; Section 2.6 presents the design process of the hardware steganography process for DSP cores; Section 2.7 analyses security properties of hardware steganography; Section 2.8 presents an analysis and comparison of hardware steganography with watermarking for different DSP IP cores; finally, Section 2.9 concludes the chapter.
This chapter discusses forensic detective control using a digital signature-based watermark for intellectual property (IP) cores or integrated circuits (ICs). The chapter provides detailed insight on digital-signature generation and the embedding process that includes a discussion on signature-generation rules and algorithms, IP core protection using forensic detective control, methodology of implanting digital signature -based watermark constraints covertly into an IP core design and its respective design process.
This chapter discusses forensic detective control using digital signature-based watermarks for fault-secured digital signal processing (DSP) cores or integrated circuits. The chapter provides detailed insight on the utility of the digital signature process for fault-secured DSP cores, which is an extension of Chapter 3. This chapter includes a discussion on transient fault security, generating loop unrolled control data flow graphs representing DSP cores, fault-secured IP core protection using forensic detective control of a digital signature, the methodology of implanting digital signature - watermarking constraints covertly into an IP core design, and the respective design process. The chapter is organized as follows: Section 4.1 introduces the background to IP cores and their countermeasures as well as the background on fault-secured IP cores; Section 4.2 discusses the threat model for which a digital-signature approach is applicable; Section 4.3 provides a discussion on contemporary IP core-protection approaches for DSP cores; Section 4.4 explains forensic detective control using a digital signature-based watermark; Section 4.5 presents a case study of the digital signature process for securing fault-secured FIR filters; Section 4.6 presents an analysis and comparison of digital signature-based watermarks for various fault-secured DSP cores; Section 4.7 concludes the chapter.
The chapter describes a multi-level watermarking process for intellectual property (IP) cores that leverages the electronic-system level (ESL) and register-transfer level (RTL). A detailed elaboration is provided on the salient features of this multilevel watermarking approach followed by its encoding technique, embedding process, detection process and, finally, implementation details using case studies. The chapter is organized as follows: Section 5.1 discusses the abstraction levels of a digital design followed by some IP protection basics; Section 5.2 introduces some of the prior works in this domain; Section 5.3 presents the salient features and advantages of a multi-level watermarking process; Section 5.4 explains the signature-embedding process for digital signal processor (DSP) cores; Section 5.5 discusses the design process of a multi-level watermarked IP core using a finite impulse response (FIR) filter; Section 5.6 presents the signature detection details of a multi-level watermark; Section 5.7 presents an analysis based on case studies; Section 5.8 concludes the chapter.
This chapter describes a cryptosystem-based fingerprinting approach for IP cores that is employed during the register allocation phase of electronic-system level synthesis. The need for a buyer's fingerprint and its desirable features are highlighted. Further, a detailed elaboration on the fingerprint selection and encoding technique followed by the embedding process and, finally, implementation details on case studies are provided. The chapter is organized as follows: Section 6.1 discusses the various challenges in electronic system design, followed by some fingerprint basics; Section 6.2 introduces some of the prior works in this domain; Section 6.3 presents an overview of the crypto-based fingerprinting process; Section 6.4 illustrates in detail the fingerprinting approach for digital signal processing (DSP) cores; and Section 6.5 discusses the security and design cost analyses using different case studies.
This chapter discusses a multi-phase obfuscation process for fault-secured intellectual property (IP) cores during electronic system level (ESL) synthesis. A detailed elaboration on the threat model for fault-secured IP cores is followed by the use of the multi-phase obfuscation process for digital signal processing (DSP) circuits and, finally, analyses of case studies. The chapter is organized as follows: Section 7.1 discusses fault-secured IP cores and their needs, followed by different threats to fault-secured IP cores and how to solve them. Section 7.2 focuses on the differences between functional obfuscation and structural obfuscation. Section 7.3 presents the problem formulation for protecting fault-secured IP cores. Section 7.4 discusses selected contemporary structural obfuscation approaches used to date. Section 7.5 provides an overview of the multi-phase obfuscation approach followed by evaluation models used and details of the approach in the context of fault-secured DSP circuits. Section 7.6 demonstrates the multi-phase obfuscation approach on a fault-secured finite impulse response (FIR) filter. Section 7.7 presents analyses based on case studies. Section 7.8 concludes the chapter.
This chapter highlights an alternative paradigm for the design of structurally obfuscated digital signal processing (DSP) cores inspired by security hologram. Discussion on different structural-obfuscation techniques have been included in this chapter with emphasis on the algorithms used for obfuscation during design synthesis of high-level synthesis (HLS). The chapter is organized as follows: Section 8.1 introduces the importance of obfuscation for IP cores during the system-on-chip design process; Section 8.2 discusses the background on security hologram; Section 8.3 highlights the possible use of applying the hologram concept for structural obfuscation; Section 8.4 explains the hologram-based obfuscation methodology for DSP cores; Section 8.5 presents illustrative examples for hologram-based obfuscation on DSP cores; Section 8.6 discusses the process of determination of gate count for un-obfuscated and obfuscated designs; Section 8.7 presents a demonstration and examples of high-level transformation-based obfuscated DSP circuits; Section 8.8 presents design examples of un-obfuscated (baseline) DSP circuits; Section 8.9 presents analysis on case studies; Section 8.10 concludes the chapter.
This chapter discusses the security of functionally obfuscated digital signal processing (DSP) cores. Some of the most prominent aspects of this chapter include descriptions of the attack models, points of vulnerability for launching reverse engineering (RE), security properties of the functional-obfuscation process, security against removal attack in the context of DSP cores, hardware-design methods of various state-of-the-art security solutions and a comparative perspective of different approaches used in the context of DSP cores.
