Phase-locked frequency generation and clocking covers essential topics and issues in current Phase-Locked Loop design, from a light touch of fundamentals to practical design aspects. Both wireless and wireline systems are considered in the design of low noise frequency generation and clocking systems. Topics covered include architecture and design, digital-intensive Phase-Locked Loops, low noise frequency generation and modulation, clock-and-data recovery, and advanced clocking and clock generation systems. The book not only discusses fundamental architectures, system design considerations, and key building blocks but also covers advanced design techniques and architectures in frequency generation and clocking systems. Readers can expect to gain insights into phase-locked clocking as well as system perspectives and circuit design aspects in modern Phase-Locked Loop design.
Inspec keywords: digital phase locked loops; clocks; voltage-controlled oscillators; clock and data recovery circuits; FIR filters; field effect MIMIC; optical links; LC circuits; phase noise; direct digital synthesis; CMOS digital integrated circuits; multiplying circuits; electromagnetic interference; elemental semiconductors; time-digital conversion; field effect MMIC; transceivers; millimetre wave oscillators; phase locked oscillators; clock distribution networks; silicon; MMIC oscillators; submillimetre wave integrated circuits; low-power electronics; frequency modulation; submillimetre wave oscillators; charge pump circuits; frequency locked loops
Other keywords: multiplying DLL; DTC-based subsampling PLL; clock data recovery; modern circuit architectures; digital clock circuit; spread spectrum clock generator; millimeter wave; integrated LC oscillators; low-noise frequency modulation; phase-locked frequency generation; high-performance CMOS clock distribution; fully synthesized digital PLL; data recovery circuits; word length 1 bit; clock-and-data recovery; optical links; CDR; low-cost EMI solution; wireless systems; ultra-high-speed wireline transceivers; time-to-digital converters; 1b high-pass modulation; fractional-N frequency synthesis; ultra-low-power ADPLL; digital-intensive phase-locked loops; monolithic phase-locked loops; spur mitigation techniques; phase-locked frequency clocking; mm-wave CMOS VCO; sub-THz CMOS VCO; time amplified charge pump PLL; bang-bang digital PLL; low-noise synthesis; modern wireless architectures; hybrid PLL; hybrid two-point modulation; wide locking range; modern wireline systems; advanced clock-frequency generation; embedded FIR filtering; nested frequency-locked loop; ultra-low phase noise ADPLL; silicon-based THz frequency synthesizers; sub-sampling PLL techniques; DPLL architecture; low-noise frequency generation; clock-and-data clocking; wideband PLL
Subjects: Microwave circuits and devices; Power electronics, supply and supervisory circuits; Digital filters; Digital electronics; Modulation and coding methods; Textbooks; Modulators, demodulators, discriminators and mixers; Electrical/electronic equipment (energy utilisation); Oscillators; Radio links and equipment; Electromagnetic compatibility and interference; Telecommunication systems (energy utilisation); General electrical engineering topics; Semiconductor integrated circuits; Optical communication
The phase-locked loop (PLL) is a key building block in both wireline and wireless systems. In the wireline system, low-jitter clock generation and clock-and-data recovery (CDR) circuits are critical in high data rate I/O links. In the wireless system, the delta-sigma (DS) fractional-N frequency synthesizer plays an important role in modern transceivers not only as a local oscillator but also as a phase modulator with direct-digital modulation. Due to various applications, diversified PLL architectures and circuit techniques have been proposed in consideration of performance, power, and cost, making it difficult for circuit designers to choose the right design solution. Hence, it would be somewhat helpful for circuit designers to gain a historical view of the PLL integrated circuit. This chapter reviews major innovations in the development of early-stage complementary-metal-oxidesemiconductor (CMOS) PLLs. In the first section, a brief overview of the development of PLL integrated circuits (ICs) is introduced. Then, major innovations in the history of CMOS PLLs are described in the following sections by considering architecture, circuit, and application aspects.
Fractional-N PLLs, particularly delta-sigma fractional-N PLLs, are some of the most popular integrated frequency synthesizers. They offer very fine grain frequency synthesis and find use in a wide range of applications such as LO synthesis, phase/frequency modulation, spread-spectrum clocking, frequency hopping, etc. While very useful, fractional-N PLLs present interesting technical challenges in the form of excess phase noise and fractional spurs. However, with the help of clever quantization noise shaping techniques and careful circuit design, phase noise and spurious tone performance close to integer -N PLLs can be achieved without sacrificing their attendant benefits.
With shrinking unit intervals (UI), the optimal horizontal centering of the reference sampling point becomes an important consideration for the choice of the phase detector and associated timing recovery method. Optimization of the timing recovery and link equalization can be greatly enhanced by the proper choice of timing function which, in conjunction, with proper equalization techniques will greatly improve the system performance. The material in this chapter has presented an overview of some of the considerations involved in the choice of phase detectors for good horizontal centering as well as good dynamic tracking characteristics and has introduced some analysis techniques to make quantitative comparisons to enable architectural decisions.
In this chapter, we present a 300-GHz frequency synthesizer incorporating a triple-push VCO with a Colpitts-based active varactor (CAV) and a frequency divider with three-phase injection [24]. The synthesizer, implemented in 90-nm SiGe Bipolar complementary-metal-oxide-semiconductor (BiCMOS) with half of 240/315 GHz, achieves 7.9% of locking range (280.32-303.36 GHz) and generates -14 dBm of output power at 290 GHz. Based on the measurement result, the frequency -scaled phase noise of the 294.9-GHz signal is -77.8 dBc/Hz (-82.5 dBc/Hz) at the 100 -kHz (1 MHz) offset.
Integrated circuits, especially analog circuits, are highly sensitive to process, voltage, and temperature (PVT) variations. The information processed by analog circuits is often embedded in the amplitude of the waveforms, which requires circuits with high precision and high linearity. On the other hand, analog signal processing in time domain, such as (TDCs) and digital to-time converters (DTCs), was not widely adopted until the late 1990s when semiconductor technology advanced to the sub-micrometer region.
BB digital PLLs, thanks to the use of a single-bit TDC, i.e. a BBPD, dissipate much less power than their counterparts employing a multi-bit TDC. The main issues related to the adoption of such a hard nonlinearity in the loop, i.e. how to avoid limit cycles in fractional-mode so as to obtain a wireless-class output spectrum, how to control the bandwidth, and how to guarantee a fast lock, have been discussed. We have shown that digitally intensive architectures enable powerful calibration circuits, mostly based on LMS techniques, to solve these issues, even in the presence of PVT variations.
Modern phase-locked loops (PLLs) can generally be categorized as either digital or analog; in this chapter, we will describe hybrid PLLs, in which we attempt to combine the best features of both. With this goal in mind, let us first discuss the two approaches with a view to gaining an understanding of the benefits and limitations of each approach.
This chapter provides an overview of the generation of PLL spurs and their potential impact on wireless and wireline the system. In order to mitigate the spurs, the new DSP-assisted technique can be applied in the digital PLL platform to push the performance limit beyond the analog PLL capability. Two design examples with direct spur mitigation and dither-based spur mitigation techniques are introduced to demonstrate the efficacy of these DSP techniques. With more advanced technology to come and accommodate their advantage for faster digital computation, it is expected that DSP-assisted techniques, also summarized in [27], will enable the larger-scale adoption of this DPLL architecture in the design community.
As CMOS technology scaling advances, traditional analog circuits have moved toward digital -intensive or all -digital designs during the past few years. While taking advantage of digital circuits in scaled complementary metal -oxide -semiconductor (CMOS) technology, digital -intensive or all -digital designs still cannot be absorbed in advanced design automation used by digital very -large-scale integration circuits. This chapter investigates a design methodology for analog circuits that is referred to as synthesizable analog design. In this design methodology, all circuit building blocks are implemented in all -digital architecture and expressed in a hardware description language (HDL), which can then be synthesized from commercial standard -cell libraries and automatically perform place and route (P&R) using electronic design automation tools.
To realize ULP fractional-N ADPLL with low jitter and low spurs, the first-order DSM-based fractional controller works in conjunction with a highly linear DTC. The rms jitter can be improved when compared to using higher-order DSM, and for this a DTC with high linearity is required. To realize a linear and high-energy efficient DTC, an isolated constant-slope method is proposed. Thanks to the isolated operation of DTC, the proposed DTC can potentially work at a high sampling frequency with small power consumption while maintaining good linearity with high energy efficiency. Furthermore, the auto-zero offset switch mitigates part of the supply noise, which can improve the linearity in SoC environment. The proposed fractional-N ADPLL achieves good fractional spurs while maintaining a low jitter performance and low power, which proves the linearity and power efficiency of the DTC. The gain calibration of TA demonstrates a steady in-band phase noise of the ADPLL over the temperature variations. The measurement of lock time proves the effectiveness of the always-on coarse PLL in the feedback loop.
The integrated inductor capacitor (LC) oscillator is one of the main oscillator topologies to generate low-noise local oscillator (LO) signals in wireless transceivers. Compared to inductor-less oscillators, such as the ring oscillator or the relaxation oscillator, the LC oscillator can achieve better phase noise and figure of merit (FOM) due to its high Q resonant tank. Figure 11.1 shows LC oscillators in modern radio frequency (RF) transceivers functioning as LO signal generators that drive the down conversion mixers in the receiver and the up conversion mixers in the transmitter.
Millimetre-wave (mm-Wave) and sub-terahertz (sub-THz) oscillators are the most critical elements of mm-Wave/sub-THz signal-generation systems as their performance, in terms of tuning range, phase noise and output power, significantly affects the system performance. With the continuous scaling of the complementary metaloxide-semiconductor (CMOS) technologies, the realization of the fundamental CMOS voltage-controlled oscillators (VCOs) operating at mm-Wave/sub-THz frequency ranges has made understanding more feasible and attractive. However, it is still very challenging for fundamental oscillators to achieve a wide frequency tuning range with low phase noise and low power consumption at such high frequencies. This chapter discusses and demonstrates mm-Wave and sub-THz oscillators using magnetic tuning techniques, for both coarse and fine frequency tuning, to achieve a wide tuning range, low phase noise and low power consumption.
Millimeter-wave (mm-wave) frequency synthesizers in complementary metal oxide-semiconductor (CMOS) suffer from poor phase noise (PN), limited tuning range (TR) and high-power consumption. They are the key subsystems that typically limit the performance of mm-wave transceivers. This chapter presents a new architecture for mm-wave frequency synthesis that improves its PN performance and power efficiency. Various different techniques are introduced and demonstrated in a 60-GHz fractional-N all-digital phase-locked loop (ADPLL).
This chapter reveals techniques for fractional-N synthesis and phase/frequency modulation using the subsampling loop. A digital-to-time converter (DTC) is applied at the input of the system to enable compensation of fractional/modulation phase residue. We will discuss how the original characteristics of a subsampling PLL can be preserved by careful DTC design and power-efficient predistortion. The concepts explored are proven with measured performance of a prototype implemented in bulk 28 nm complementary metal-oxide-semiconductor (CMOS). The PLL operates with almost no performance gap (176/198 fs RMS jitter) between the integer and fractional operation, achieving up to -247.6 dB FOM. The designed loop is also capable of two -point, 10 Mbit/s Gaussian minimum shift keying (GMSK) modulation with measured -40.5 dB error vector magnitude (EVM) around a carrier of nearly 10 GHz. This chapter is based on the material reported.
This chapter presents a hybrid two -point modulator architecture based on the semi digital phase -locked loop (PLL). By utilizing a 1 -bit AE modulation (DSM) with embedded fmite-impulse response (FIR) filtering, the high-pass modulation path does not suffer from the digitally controlled oscillator (DCO) gain nonlinearity. The digital FIR filter in the high-pass modulation path not only suppresses quantization noise but also reduces noise coupling with time -interleaved switching of partitioned capacitors. In addition, the proposed two -path DCO modulation enables a fl exible gain partition for the high-pass and low-pass modulation path within the DCO. To further enhance the linearity of the fractional -N PLL and the modulator, a hybrid FIR filtering method is used for the low-pass modulation path. The chapter gives two design examples to validate the proposed two -point modulation: A 1.8-GHz two -point modulator based on a semi -digital PLL implemented in 65 nm complementary metal -oxide -semiconductor transistor (CMOS and the 2.4-GHz two -point modulator implemented in 0.18 μm CMOS). The proposed architecture is useful for low-cost phase modulator design without requiring complex calibration algorithm or an advanced CMOS technology, while achieving comparable modulation performance.
A survey of recent developments of clock data recovery (CDR) solutions in ultrahigh-speed wireline transceivers. Design trade-offs between performance, power, and silicon area. CDR design considerations for non-return-to-zero (NRZ) and pulse- amplitude-modulation (PAM-4) signal modulation schemes and silicon examples.
This chapter focuses on the design of energy -efficient CDR circuits for highspeed optical links. In the first part, a BMCDR is introduced [3]. It incorporates a selective gating ring oscillator in a phase -locked loop (PLL). The selective gating oscillator is running at 1/n data rate, which enables high-speed operation with low power consumption. Meanwhile, the proposed BMCDR manifests both the advantages of instant phase locking and data jitter suppression in contrast to conventional gating -only or PLL-only CDRs. In the second part, a fully integrated optical receiver consisting of an integrating -type receiver front-end and a new baud -rate CDR is described [4]. A hybrid loop fi lter is proposed to facilitate programmable bandwidth with a constant phase margin. Both the experimental prototypes have small form factors and high energy efficiency. They demonstrate strong potentials to be applied in consumer electronics and high-performance computing platforms.
In this chapter, we mostly discussed 2X oversampling digital CDRs, which required multiple high-frequency clock phases for data and edge sampling. In contrast, baud-rate CDRs employ a single clock phase for data and clock recovery, thereby reducing the power consumed in multiphase clock generation and distribution circuits. Interested readers can read more about baud-rate CDRs, their benefits and drawbacks.
In this chapter, spread spectrum clock generation (SSCG)-an advanced clock generation solution for electromagnetic interference (EMI) -is presented. EMI becomes critical as the clock speed and the degree of integration are increased. Various EMI suppression techniques are introduced in this chapter. Among EMI suppression techniques, SSCG is a simple but cost-effective solution since it requires no external components and can be implemented using existing clock generators. Several SSCG design approaches are described. Similar to other clock generators, SSCG also faces implementation issues, for example, noise, non linearity, and mismatch. Finally, recent spread spectrum clocking (S SC) modulation profiles are presented and discussed because the SSC modulation profile dominates the EMI performance.
In this chapter, we provided background on three major jitter sources in high performance CMOS clock distribution: power supply induced jitter (PSIJ), random jitter (RJ), and jitter amplification. We discussed how PSIJ is introduced in the CMOS inverter and its accumulation along a chain of buffers depending on the type of supply noise and its variation along the buffer chain. We also reviewed the analysis of RJ in the CMOS inverter. We described design tradeoffs to minimize both PSIJ and RJ in global clock distribution. We described linear models of jitter amplification, including the jitter impulse response (JIR) and jitter transfer function (JTF). Jitter amplification for buffers driving transmission -line interconnect was analyzed quantitatively, and simulations were used to develop insight. Design guidelines are also given for both cases. Finally, we discussed design considerations for jitter amplification in CMOS clock distribution. With the increasing use of CMOS circuits for high-performance clock distribution in advanced CMOS technologies, we believe the methods and guidelines in this chapter will prove ever more useful.
The phase-locked-loop (PLL) is a ubiquitous component in modern ICs due to its versatility. It can, for instance, be used for clock generation, frequency synthesis, frequency modulation and demodulation, clock and data recovery, synchronization, and spread spectrum signal generation, in applications like high-performance analog-to-digital converters, wireline and optical transceivers, and wireless radio transceivers. Of the many known PLL architectures, the one shown in Figure 21.1(a) is perhaps the most widely used which we call the "classical PLL" architecture. It consists of a voltage -controlled oscillator (VCO) locked to a reference clock Ref by a feedback loop with the following "loop components": a phase detector (PD), a charge pump (CP), a loop filter (LF), and a frequency divider with ratio N (÷N). Jitter (or phase noise) and power are often the two critical performance matrix for many PLL applications. With the trend of higher data -rate, higher carrier frequency and higher order of modulation, the jitter or phase noise requirement becomes more and more demanding while the power budget is still limited. The PLL's jitter performance for a given power can be evaluated with the PLL jitter and power figure-of-merit (FOM) [1]. In the classical PLL, the PD and CP noise is multiplied by N2 and often dominates the in -band phase noise, thus limiting the achievable PLL FOM.
Phase locked loop (PLL) is a feedback control system that has been used for several decades. As the feedback control loop is quite straight forward, architectural innovations in PLLs have been rather limited. Most PLLs are based on either type-I or type-II control systems and it is usually the circuit implementations that improve their performance. In this chapter, we explore architectural innovations in a PLL, by using additional feedback loop to gain further advantages in performance such as jitter, power consumption, and immunity to supply-noise. In Section 22.1, we look at how a reference-less frequency locked loop (FLL) around the VCO has the potential to improve the phase noise of a VCO. In Section 22.2, we investigate how the FLL-based VCO can be used in a digital PLL for optimal performance in power and noise. Finally, in Section 22.3, we will investigate how this architecture can be used to mitigate jitter due to supply noise.
This chapter introduces a time-amplified charge-pump PLL (TAPLL) which uses a low-noise time amplifier (LNTA) to amplify time difference between a reference clock and a feedback clock all digitally. TAPLL can achieve low in-band noise because the input-referred noise of the loop is divided by the gain of LNTA. Moreover, the bandwidth of PLL can be extended with noiseless circuits to achieve low in-band noise which is one of important keys to implement a wide-band PLL. This chapter is arranged as follows: First, the noise of a charge pump PLL is discussed, and then design of TAPLL is disclosed followed by the implementations of LNTA and a self-regulated ring oscillator. Finally, a ring oscillator-based TAPLL is measured to demonstrate the superiority of the architecture.
The modern SoC chip usually requires multiple clock generators that can achieve low jitter performance over a wide frequency range with the compact area and low power consumption. The multiplying delay-locked-loop (MDLL) employing a ring voltage-controlled oscillator (VCO) is a promising solution to fulfill all these requirements. This chapter focuses on the design of ring-VCO-based MDLL that can achieve low-jitter and spur performance across a wide frequency tuning range in the presence of process-voltage-temperature variations.
RF synthesis has generally shied away from ring oscillators due to their much more severe phase noise-power trade-offs than those of inductor-capacitor (LC) topologies. Today's multiband, multimode radios, however, require a number of synthesizers and can greatly benefit from compact, flexible implementations afforded by ring oscillators. This chapter proposes several phase-locked loop (PLL) architectures that can achieve a wide loop bandwidth, thus suppressing the voltage-controlled oscillator (VCO) phase noise and allowing the use of a ring topology. The concepts are demonstrated for both integer-N and fractional-N RF synthesis. Most of the concepts introduced here are applicable to other PLL and oscillator topologies as well. This chapter is organized as follows. In Section 25.1, we describe an integer-N synthesizer that achieves a phase noise of -114 dBc/Hz at 10-MHz offset with a spur level of -65 dBc [1]. In Section 25.2, we introduce a new fractional-N synthesizer architecture that achieves a loop bandwidth (BW) as large as fREF/4 [2].