IP Core Protection and Hardware-Assisted Security for Consumer Electronics
2: University of North Texas, USA
IP Core Protection and Hardware-Assisted Security for Consumer Electronics presents established and novel solutions for security and protection problems related to IP cores (especially those based on DSP/multimedia applications) in consumer electronics. The topic is important to researchers in various areas of specialization, encompassing overlapping topics such as EDA-CAD, hardware design security, VLSI design, IP core protection, optimization using evolutionary computing, system-on-chip design and application specific processor/hardware accelerator design. The book begins by introducing the concepts of security, privacy and IP protection in information systems. Later chapters focus specifically on hardware-assisted IP security in consumer electronics, with coverage including essential topics such as hardware Trojan security, robust watermarking, fingerprinting, structural and functional obfuscation, encryption, IoT security, forensic engineering based protection, JPEG obfuscation design, hardware assisted media protection, PUF and side-channel attack resistance.
Inspec keywords: industrial property; consumer electronics; supply chains; security; digital signal processing chips; reverse engineering
Other keywords: IP core protection; intellectual property; hardware fingerprinting; design supply chain; hardware watermarking; computational forensic engineering; reusable digital signal processing IP cores; hardware obfuscation; hardware metering; brute-force attacks; energy consumption; physically unclonable functions; watermarked AES; side channel attacks; structural obfuscation; Trojan horse attacks; consumer electronics; backdoor attacks; ownership issues; functional obfuscation; hardware AES; hardware protection; reverse engineering attacks; hardware-assisted security; DSP cores
Subjects: Security aspects of hardware; General and management topics; General electrical engineering topics; Digital signal processing chips; Legal aspects of computing; Digital signal processing chips
- Book DOI: 10.1049/PBCS060E
- Chapter DOI: 10.1049/PBCS060E
- ISBN: 9781785617997
- e-ISBN: 9781785618000
- Page count: 506
- Format: PDF
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Front Matter
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1 Introduction to IP core protection and hardware-assisted security of consumer electronics
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This chapter presents an overview of the book and discussions on topics that could serve as an introductory part toward the overall content of the book. It is assumed that the readers will have some subject knowledge on topics such as very large scale integration (VLSI), embedded systems, hardware design flow, etc., before adopting the section of this book.
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2 Security in consumer electronics and internet of things (IoT)
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In a typical consumer electronics generation, diverse forms of attacks exist, e.g., system security, information security, information privacy, system trustworthiness, hardware IP protection, information copyright protection. Each of the attacks have their own threats and serve different purposes. The objective of this chapter is to differentiate each of these attacks in the context of internet of things (IoT). IoT is a very hot, trending topic of research, where different devices, sensors, and computers are connected to a network, collect data, and process for different purposes. A network of devices and sensors connected to the cloud can complete many unimaginable tasks, and without the existence of cloud, almost all task would have been very difficult to achieve and complete. Since, most connectivity occurs in cloud, there is always a probability of security and privacy threats. Because all types of the different devices are connected to the internet, attackers pose a huge threat to the system. For example, if any electronic system that is responsible for home care, healthcare, running an entire city, etc., are attacked, then the consequence of this threat will be a major catastrophe.
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3 Trojan security aware DSP IP core and integrated circuits
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This chapter discusses different security approaches to designing digital signal processing (DSP) cores that have detection capability against functional-type hardware Trojans in a global supply chain. In the current design and fabrication supply chain, design houses, circuits and system core vendors, and manufacturing houses are globally scattered. It is quite possible that Trojans can be inserted in this design and manufacturing supply chain by anyone involved at any phase. Such Trojans can give backdoors to hackers and affect the operation of the system that uses the infected hardware. In a worst case, in critical applications, such as aircrafts and medical devices, functioning can be completely stopped, causing catastrophic consequences.
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4 IP core and integrated circuit protection using robust watermarking
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This chapter discusses robust watermarking approaches for the ownership protection of hardware cores [a.k.a. intellectual property (IP) cores]. Watermarking ensures some additional attributes inserted in the hardware core such a way that it can be used to verify ownership of the hardware core when required. Robust watermarking approaches have been discussed as these are resilient to various attacks that happen in global supply chain for various reasons.
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5 Symmetrical protection of DSP IP core and integrated circuits using fingerprinting and watermarking
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This chapter discusses the use of watermarking and fingerprinting for symmetrical protection of DSP IP cores and integrated circuits. Symmetrical IP core protection is a mechanism in which both seller and buyers of an IP can have signature for doubleproof of ownership and whereas significantly reducing false ownership claims.
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6 Computational forensic engineering for resolving ownership conflict of DSP IP core
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The article focuses on a technique called computational forensic engineering (CFE) for ownership protection. FE extracts the features of DSP IP cores and matches to statistically suggest the original ownership. It also discusses various steps involved in CFE hard IP core and presents specific details with case study examples.
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7 Structural obfuscation of DSP cores used in CE devices
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Previous chapters, watermarking, fingerprinting, and forensic engineering have been discussed for resolving various ownership-related problems. This chapter discusses structural obfuscation approaches to thwart IP piracy and reverse engineering (RE). This approach, when effective, can save billions of dollars of revenue losses in CE and semiconductor industry. Especially, a multi-high-level transformation-based structural obfuscation process has been presented for DSP IP cores as hardware-hardening technique. The chapter is structured as follows: Section 7.2 highlights the fundamentals of obfuscation with stress on structural obfuscation; Section 7.3 discusses different compiler transformation-driven structural obfuscation methodology. Section 7.4 discusses low-cost structurally obfuscated design exploring technique. Section 7.5 demonstrates a multistage structural obfuscation technique through a motivational example. Section 7.6 presents the results of a case study.
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8 Functional obfuscation of DSP cores used in CE devices
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The previous chapter detailed many approaches for structural obfuscation but we now move forward to another class of obfuscation called “functional obfuscation.”The use of either of the techniques is the choice of design engineers. This chapter presents several methods to thwart IP piracy and RE attacks through functional obfuscation. More specifically, we will discuss IP functional locking blocks (ILBs)-based logic obfuscation for DSP cores used in CE devices as hardware hardening technique (Sengupta et al., 2018). Moreover, a PSO-based DSE is performed to generate a low-overhead, functionally obfuscated (FO) design solution for DSP cores (Sengupta and Sedaghat, 2011, 2013). The rest of the chapter is organized as follows: Section 8.2 discusses different attack scenarios and threat model. Section 8.3 explains selected functional obfuscation techniques that are available in the literature. Section 8.4 discusses the design process of functional obfuscation for DSP IP cores used in CE devices. Section 8.5 presents the security analysis of functional obfuscation methodology for DSP IP core design. Section 8.6 discusses PSO-based optimization for FO design. Section 8.7 presents analysis on case studies/test cases.
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9 Obfuscation of JPEG CODEC IP core for CE devices
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Joint Picture Export Group (JPEG) is the most commonly used image compression standard in the world. One cannot comprehend a CE system that does not process a JPEG. Without JPEG there is no smartphone photography, no social media. So, authors feel strongly that this important multimedia core “JPEG”needs to give well-deserving credit in terms of securing it when security/protection of “DSP core”has been a major focus of all the discussions in this book so far. The chapter is organized as follows: Section 9.2 provides an overview of DCT-based JPEG compression and decompression process. Section 9.3 explains the design process of generating structurally obfuscated JPEG CODEC IP core; Section 9.4 provides a detailed insight on the implementation process of obfuscated JPEG codec IP core in a CAD synthesis tool. Section 9.5 provides implementation and analysis of JPEG CODEC IP core as well as compressed images through the devised JPEG CODEC IP core.
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10 Advanced encryption standard (AES) and its hardware watermarking for ownership protection
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In this era of consumer electronics, cyber security is one of the key challenges. Any security, privacy, or protection methods that are deployed rely on cryptography. Advance encryption standard (AES) is one of the heavily used cryptography algorithms for its advantages. This chapter is dedicated to the process of AES and its hardware design in the form of IP core. Several hardware security techniques rely on AES IP core as an important block. Additionally, since this is such an important core, its self-protection against forgery/piracy is also crucial. Thus, this chapter will also discuss about AES IP core protection using watermarking.
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11 Hardware approaches for media and information protection and authentication
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Technology scaling has allowed us to design high-performance devices with a lowpower consumption. The advent of IoT has increased the versatility of data collection and there are many different ways of collecting and transferring data over the Internet. The data that is being collected is also in different forms, that is, text, images, videos, and audios. When they are shared, for a legit use, attackers can break the security and use them for illegible purposes or claim ownership to sell them commercially. This has been the trend lately where many counterfeit products are appearing in the market. This section discusses the digital watermarking, different schemes of digital watermarking, and how a media object can be secured using a watermark. They are also not completely resistant to attacks and measures need to be taken to secure the content that is being watermarked. The chapter also presents different issues with the watermark implementations, attacks and countermeasures to those attacks on watermarking. Section 11.1 presents a broad overview of the IP protection. Section 11.2 discusses the generic overview and components of any watermark system. Section 11.3 summarizes various types of watermarks. Section 11.4 discusses various applications of watermarking. Section 11.5 presents desired characteristics of watermarks. Sections 11.6 discusses the technical challenges of the watermarking. Section 11.7 discusses hardware-based watermarking systems available in the current literature. Section 11.8 discusses about watermarking in smart vehicles. Section 11.9 discusses about medical signal authentication. Section 11.10 highlights side-channel information leakage and its countermeasures. Section 11.11 outlines various forms of attacks on watermarks and watermarking systems. Section 11.12 presents the difficulties involved in making use of them in practice.
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12 Physical unclonable functions (PUFs)
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It has been the practice to store information under lock and key for safeguarding it. Even today, we use cryptographic primitives to store information securely under lock and key, encryption, and decryption. For the process of cryptography, keys are necessary for any operation. But these keys should be stored in the memory so that they can be used whenever necessary. When a key is stored in the memory, it can be stolen by the adversary using various methods. Therefore, storing it in a nonvolatile memory is not an option in this age of security threats. Physical unclonable functions (PUFs) are the promising security primitives used for generating the keys instead of storing them in the memory. These modules use the naturally occurring manufacturing variations in the fabrication process for generating the keys for cryptographic purposes. This chapter discusses different types of PUFs. Section 12.1 gives a brief introduction of PUFs. Section 12.2 discusses working principles of PUFs. Section 12.3 discusses different characteristics of a PUF design. Section 12.4 presents different classifications of PUFs. Various designs of PUF based on ring oscillators (ROs) are presented in Section 12.5, based on multiplexers and reconfigurability are presented in Section 12.6. Static random access memory (SRAM)-based PUFs are presented in Section 12.7, memristor-based PUFs are presented in Section 12.8, and diode-based PUFs are presented in Section 12.9. There are also non-silicon-based PUF designs, such as carbon PUFs, presented in Section 12.10. Microprocessors can also be used for implementing the PUF designs which are presented in Section 12.11. Magnetic material-based PUFs are presented in Section 12.12 and the FPGA implementations of PUF and security measures for FPGA are presented in Section 12.13. Some case study applications are presented in Section 12.14. Further the issues and challenges faced during the design of PUF modules are presented in Section 12.15. The conclusion and future directions are presented in Section 12.16.
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Appendix A
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This appendix describes the derivation process of the Haar wavelet transformation (HWT) CODEC data flow graph using Sengupta-Roy HAAR Computation Reduction Functions.
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Appendix B
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The Appendix considers transfer functions and the control data flow graph of DSP cores including: four-point DCT; four-point DIT-FFT; four-point IDCT; eight-point DIT-FFT; eight-point IDCT; third-order FIR filter and third-order IIR filter.
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Back Matter
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