Electronics has always been a fight against noise. Because an electrical signal is generally expressed in a two-dimensional way, such as voltage (or current) in y-axis and time in x-axis, the noise can also be classified into two primary types, such as voltage noise and timing noise. For an analog signal, the voltage noise is much straightforward to understand since it is directly related to signal-to-noise ratio (SNR). However, for a digital signal, because of the inherent noise margin of a digital complementary metal-oxide semiconductor (CMOS) circuit, all of the noise components within the noise margin are removed and the digital signal is restored intact. However, the noise injected during the transition of digital signal is converted to the timing noise, instead of being removed. This book explains the various effects of jitter and its frequency-domain representation and phase noise, which are two different notational metrics that quantify the timing noise of a signal, and focuses on describing circuit techniques to achieve a low phase noise and jitter.

In definition, an electronic oscillator is an electronic system consisting of active and passive circuit elements to produce a periodic signal at the output without the application of an external input signal [1]. Because an oscillator itself generates a periodic signal, specifically a clock signal, the spectral purity of the signal highly depends on the quality of the oscillator. Even a standalone oscillator can serve as a clocking circuit depending on the system requirement. Therefore, a CMOS oscillator is the most important building block of a CMOS clocking circuit that should be studied in depth. This chapter will introduce fundamentals of two popular CMOS oscillator topologies: LC oscillator and ring oscillator.

In Chapter 4, we studied the phase noise of electrical oscillators. As described in Chapter 4, the frequency instability of an oscillator diverges at a low frequency. It limits the use of the oscillator standalone as a clocking circuit in many applications. To address that, a negative feedback system is generally utilized to correct the instability of the oscillator. A phase -locked loop (PLL) forms a negative feedback loop where an oscillator -generated signal is frequency- and phase -locked to a reference signal. Just like any feedback loop, a PLL comprises of producer, sensor, and loop filter. As shown in the simplified block diagram of PLL in Figure 5.1, the voltage -controlled oscillator (VCO) which generates a clock whose frequency is controlled by a voltage input serves as the producer, and the phase detector which measures the phase difference between the VCO clock and the reference clock is used for the sensor of the loop. The loop filter determines how to control the producer based on the measured value from the sensor. Because a PLL controls the frequency of the VCO to match the phase and frequency of the reference clock and the output clock, the loop filter needs to adjust both the phase and frequency so that the system should be second -order or higher. On the other hand, a delay -locked loop (DLL) uses a voltage -controlled delay line (VCDL) as the producer. Since the VCDL receives an input signal and adjust only the delay, the frequency of the reference clock and the output clock is always the same, whereas a PLL adjusts the frequency to correct the phase error. Therefore, a DLL does not have to be a second -order system. For well -designed PLLs/DLLs, the phase error is gradually corrected by the negative feedback and eventually converges to zero.

In this chapter, loop dynamics of DLLs are derived and compared with those of PLL. In general, DLLs are classified into type -I DLL and type -II DLL, according to the number of input clocks. Figure 7.1 shows simplified block diagrams of the type I and type -II DLLs. In type -I DLL, there is only one input which is fed to the VCDL, and the phase detector compares the input and the output of the VCDL. The applications of type -I DLL include multiphase clock generation and zero -delay buffer. On the other hand, there are two inputs in the type -II DLL. Whereas the same clock signal is fed to both VCDL and phase detector in the type -I DLL, one of the type -II DLL input clocks is served only as the reference signal of the VCDL but the other is used to provide a reference phase that the VCDL output clock is driven to be aligned. That is, the VCDL delays only one of the inputs, and the phase detector compares the output of the VCDL and the other input. Main application of type -II DLL is clock and data recovery circuit in mesochronous clocking receivers.

As CMOS technology scales down, several challenges have been raised which degrades the performance of the analog charge-pump PLLs. For example, the increasing leakage current of the loop filter capacitor degrades the reference spur, the decreasing output impedance of CMOS device increases the pump -current mismatch, and the severe PVT variations make it almost impossible to have the optimum loop bandwidth over the PVT variations. Note that most of the challenges are caused in the analog loop filter. Therefore, the main motivation of the all -digital PLL (ADPLL) is replacing the analog loop filter to the digital loop filter. In a strict sense, the ADPLL refers to a PLL exclusively built from digital function blocks and does not contain any passive component. In a stricter sense, all components of ADPLL are synthesizable. In general, however, a broad sense of ADPLL defmition is used such that a PLL consists of digital components (especially the digital loop filter) and digital equivalents. In this chapter, the broad sense of ADPLL will be introduced.

Frequency multiplication with a DLL is not as easy as that with a PLL; however, there have been a lot of efforts to adopt DLLs for frequency multiplication, in order to take advantage of its better jitter performance owing to less jitter accumulation. A primitive way is to utilize multiphase clock that can be generated from a type -I DLL [1]. The basic concept is that equally spaced phases at the reference frequency are processed through an edge-combining logic. The simplest example is a frequency doubler shown in Figure 11.1. Basically, we have enough edge information from the original phase (c1k0) and the DLL -generated phase (c1k90), we can produce a doubled frequency. However, any mismatch in the delay elements (i.e., DO 0 D1) or the edge combining logic (i.e., two inputs of the XOR) directly translates into duty -cycle error and deterministic jitter at the output clock. Moreover, programmable multiplication ratio is difficult to achieve.

In this appendix, a brief survey on the state-of-the-art clock generators is presented.

In this appendix, noise sources in CMOS transistors, that is, thermal noise, 1/f noise, and shot noise, are briefly reviewed [1-8]. Generally, thermal noise and 1/f noise dominate the noise of MOSFET devices in normal operation. On the other hand, shot noise does not occur in an ohmic conductor so only CMOS transistors in subthreshold region exhibit the shot noise.