As electronics continue to become faster, smaller and more efficient, development and research around clocking signals and circuits has accelerated to keep pace. This book bridges the gap between the classical theory of clocking circuits and recent technological advances, making it a useful guide for newcomers to the field, and offering an opportunity for established researchers to broaden and update their knowledge of current trends. The book begins by introducing the theory of Fourier transform and power spectral density, then builds on this foundation in chapter 2 to define phase noise and jitter. Chapter 3 discusses the theory and primary implementation of CMOS oscillators, including LC oscillators and ring oscillators, and chapter 4 introduces techniques for analysing their phase noise and jitter. Chapters 5-7 cover conventional clocking circuits; phase-locked loop (PLL) and delay-locked loop (DLL), which suppress the phase noise of CMOS oscillators. The building blocks of conventional PLLs/DLLs are described, and the dynamics of the PLL/DLL negative feedback loop explored in depth, with practical design examples. Chapters 8-11 address state-of-the-art circuit techniques for phase noise suppression, presenting the principles and practical issues in circuit implementation of sub-sampling phase detection techniques, all-digital PLL/DLL, injection-locked oscillator, and clock multiplying DLL. Extensive survey and discussion on state-of-the-art clocking circuits and benchmarks are covered in an Appendix.
Inspec keywords: jitter; hardware description languages; digital phase locked loops; voltage-controlled oscillators; multiplying circuits; integrated circuit modelling; interference suppression; CMOS integrated circuits; phase noise; clocks; network analysis; delay lock loops; injection locked oscillators; integrated circuit design; integrated circuit noise
Other keywords: clock multiplying DLL; all-digital PLL; injection locking; PLL loop dynamics; System Verilog modeling; phase noise theory; VCO; MOSFET transistor noise; clock generators; delay-locked loop; low phase noise; CMOS clocking circuits design; DLL jitter; phase-locked loop; CMOS oscillators; FoM; phase noise suppression; subsampling PLL; voltage-controlled oscillators; figure of merits; CMOS clocking circuits analysis
Subjects: Digital circuit design, modelling and testing; CMOS integrated circuits; Oscillators; Computer-aided circuit analysis and design; Other analogue circuits; General electrical engineering topics; Semiconductor integrated circuit design, layout, modelling and testing; Other digital circuits; Analogue circuit design, modelling and testing; Electromagnetic compatibility and interference
Electronics has always been a fight against noise. Because an electrical signal is generally expressed in a two-dimensional way, such as voltage (or current) in y-axis and time in x-axis, the noise can also be classified into two primary types, such as voltage noise and timing noise. For an analog signal, the voltage noise is much straightforward to understand since it is directly related to signal-to-noise ratio (SNR). However, for a digital signal, because of the inherent noise margin of a digital complementary metal-oxide semiconductor (CMOS) circuit, all of the noise components within the noise margin are removed and the digital signal is restored intact. However, the noise injected during the transition of digital signal is converted to the timing noise, instead of being removed. This book explains the various effects of jitter and its frequency-domain representation and phase noise, which are two different notational metrics that quantify the timing noise of a signal, and focuses on describing circuit techniques to achieve a low phase noise and jitter.
In this chapter, we start by defming time interval error (TIE), period jitter, and cycle -to -cycle jitter. Figure 2.1 shows the definitions of TIE, period jitter, and cycle -to -cycle jitter of a clock signal. TIE also has many different titles such as edge-to-edge jitter, time interval jitter, absolute jitter, phase jitter, or just jitter. TIE is defined as the absolute difference in the position of a clock's edge from the ideally exact position. Therefore, the ideal positions must be known or estimated to calculate TIE. On the other hand, the period jitter and cycle-to-cycle jitter do not need the ideal positions to be calculated. The period jitter, which is also called as cycle jitter, means the difference between any one measured clock period and the ideal clock period [3]. Although the period jitter definition refers to the ideal clock, its root of mean square (RMS) and peak -to -peak values are calculated statistically regardless of the ideal clock period.
In definition, an electronic oscillator is an electronic system consisting of active and passive circuit elements to produce a periodic signal at the output without the application of an external input signal [1]. Because an oscillator itself generates a periodic signal, specifically a clock signal, the spectral purity of the signal highly depends on the quality of the oscillator. Even a standalone oscillator can serve as a clocking circuit depending on the system requirement. Therefore, a CMOS oscillator is the most important building block of a CMOS clocking circuit that should be studied in depth. This chapter will introduce fundamentals of two popular CMOS oscillator topologies: LC oscillator and ring oscillator.
The term "phase noise" appeared in the world in the 1950s [1-4]. During more than 60 years after the appearance, there have been tremendous number of publications related to phase noise. For example, in December 2019, Google scholar gives more than 4.5 million results in search for "phase noise"! This number may help the readers understand how important the phase noise is. In proportional to the importance, some legendary papers which provide gorgeous theory, analysis, and insight on the phase noise are ranked in the most highly cited papers in the field of circuit design. In this chapter, we will study a few selected ones from those theories to understand and to analyze the phase noise of CMOS clocking circuit.
In Chapter 4, we studied the phase noise of electrical oscillators. As described in Chapter 4, the frequency instability of an oscillator diverges at a low frequency. It limits the use of the oscillator standalone as a clocking circuit in many applications. To address that, a negative feedback system is generally utilized to correct the instability of the oscillator. A phase -locked loop (PLL) forms a negative feedback loop where an oscillator -generated signal is frequency- and phase -locked to a reference signal. Just like any feedback loop, a PLL comprises of producer, sensor, and loop filter. As shown in the simplified block diagram of PLL in Figure 5.1, the voltage -controlled oscillator (VCO) which generates a clock whose frequency is controlled by a voltage input serves as the producer, and the phase detector which measures the phase difference between the VCO clock and the reference clock is used for the sensor of the loop. The loop filter determines how to control the producer based on the measured value from the sensor. Because a PLL controls the frequency of the VCO to match the phase and frequency of the reference clock and the output clock, the loop filter needs to adjust both the phase and frequency so that the system should be second -order or higher. On the other hand, a delay -locked loop (DLL) uses a voltage -controlled delay line (VCDL) as the producer. Since the VCDL receives an input signal and adjust only the delay, the frequency of the reference clock and the output clock is always the same, whereas a PLL adjusts the frequency to correct the phase error. Therefore, a DLL does not have to be a second -order system. For well -designed PLLs/DLLs, the phase error is gradually corrected by the negative feedback and eventually converges to zero.
In this chapter, the phase domain transfer function of each building block of the PLL is described. Because the intent of the PLL is "phase lock," the analysis should be done in the phase domain, so it is assumed that a phase error (O m ) is applied to the input of the PLL. For the derivation of the loop dynamics, Oerr is assumed to be small enough and to be introduced after the PLL achieves the phase lock.
In this chapter, loop dynamics of DLLs are derived and compared with those of PLL. In general, DLLs are classified into type -I DLL and type -II DLL, according to the number of input clocks. Figure 7.1 shows simplified block diagrams of the type I and type -II DLLs. In type -I DLL, there is only one input which is fed to the VCDL, and the phase detector compares the input and the output of the VCDL. The applications of type -I DLL include multiphase clock generation and zero -delay buffer. On the other hand, there are two inputs in the type -II DLL. Whereas the same clock signal is fed to both VCDL and phase detector in the type -I DLL, one of the type -II DLL input clocks is served only as the reference signal of the VCDL but the other is used to provide a reference phase that the VCDL output clock is driven to be aligned. That is, the VCDL delays only one of the inputs, and the phase detector compares the output of the VCDL and the other input. Main application of type -II DLL is clock and data recovery circuit in mesochronous clocking receivers.
The main idea of subsampling PLL is to remove the divider in the PLL feedback path for eliminating the noise amplification by the division factor N [1]. If the divider is removed, the phase detector should compare the reference clock and the VCO clock, whose frequencies are much different even when the PLL is locked.
As CMOS technology scales down, several challenges have been raised which degrades the performance of the analog charge-pump PLLs. For example, the increasing leakage current of the loop filter capacitor degrades the reference spur, the decreasing output impedance of CMOS device increases the pump -current mismatch, and the severe PVT variations make it almost impossible to have the optimum loop bandwidth over the PVT variations. Note that most of the challenges are caused in the analog loop filter. Therefore, the main motivation of the all -digital PLL (ADPLL) is replacing the analog loop filter to the digital loop filter. In a strict sense, the ADPLL refers to a PLL exclusively built from digital function blocks and does not contain any passive component. In a stricter sense, all components of ADPLL are synthesizable. In general, however, a broad sense of ADPLL defmition is used such that a PLL consists of digital components (especially the digital loop filter) and digital equivalents. In this chapter, the broad sense of ADPLL will be introduced.
Injection locking refers to a phenomenon that a periodic charge injection to an oscillator which leads to a frequency shift to the oscillator's free-running frequency. In specific, if the frequency of the injection signal is at the vicinity of the free-running frequency (ffree + Δj), the oscillation frequency becomes the injected frequency instead of the free-running frequency. Figure 10.1 illustrates how the periodic injection shifts the oscillation frequency. It is assumed that there is a small offset (ΔT) between the periods of the free-running oscillation and the injection pulse train. Recalling from (4.23), each pulse injection leads to the phase shift whose amount is proportional to the amount of the injected charges. That means, if the amount of the charge is large enough, the phase shift introduced by the injection is able to lag the next zero-crossing by ΔT. With the periodic pulse train, this period lag happens at every cycle, and therefore the period of the oscillation becomes Tfree ±ΔT, instead of Tfree .
Frequency multiplication with a DLL is not as easy as that with a PLL; however, there have been a lot of efforts to adopt DLLs for frequency multiplication, in order to take advantage of its better jitter performance owing to less jitter accumulation. A primitive way is to utilize multiphase clock that can be generated from a type -I DLL [1]. The basic concept is that equally spaced phases at the reference frequency are processed through an edge-combining logic. The simplest example is a frequency doubler shown in Figure 11.1. Basically, we have enough edge information from the original phase (c1k0) and the DLL -generated phase (c1k90), we can produce a doubled frequency. However, any mismatch in the delay elements (i.e., DO 0 D1) or the edge combining logic (i.e., two inputs of the XOR) directly translates into duty -cycle error and deterministic jitter at the output clock. Moreover, programmable multiplication ratio is difficult to achieve.
VCOs and PLLs have many different specifications/applications and as well have several design trade-offs, such as between the jitter, power consumption, and frequency. As a result, a figure-of-merit (FoM), which is a benchmark used to characterize the performance of a device, needs to be defmed to normalize different VCOs/PLLs performance for a fair comparison between them. Let us start with the FoM for VCO. Note that only white noise is under consideration, so we assume the phase noise is inversely proportional to the square of the offset frequency. Because it is very important to reflect the primary design trade-offs into the FoM, let us review the design trade-offs in a VCO and a PLL.
In this appendix, a brief survey on the state-of-the-art clock generators is presented.
In order to design a big system, it is very important to make a reasonable model of an analog circuit, as it is used to explore how the performance of the analog circuit affects the system performance, without running a time-consuming simulation with physical devices or gates. System Verilog is widely used in those fields for highlevel simulations including analog circuit models. In this appendix, an example of System Verilog modeling of CMOS clock generator is provided. Based on the phase noise and jitter sources of a generic clock generator that we studied in Chapter 6, we include the following jitters in the model: (1) the white (random) jitter induced from the white noise of the output buffer stage, (2) the oscillator phase noise, (3) the phase noise of reference clock, and (4) the sinusoidal jitter. Basically, the purpose of the clock jitter model is to get the phase noise profile from a designer and translate it to the actual timing perturbation.
In this appendix, noise sources in CMOS transistors, that is, thermal noise, 1/f noise, and shot noise, are briefly reviewed [1-8]. Generally, thermal noise and 1/f noise dominate the noise of MOSFET devices in normal operation. On the other hand, shot noise does not occur in an ohmic conductor so only CMOS transistors in subthreshold region exhibit the shot noise.