Although existing nanometer CMOS technology is expected to remain dominant for the next decade, new non-classical devices are being developed as the potential replacements of silicon CMOS, in order to meet the ever-present demand for faster, smaller, more efficient integrate circuits. Many new devices are based on novel emerging materials such as one-dimensional carbon nanotubes and two-dimensional graphene, non-graphene two-dimensional materials, and transition metal dichalcogenides. Such devices use on/off operations based on quantum mechanical current transport, and so their design and fabrication require an understanding of the electronic structures of materials and technologies. Moreover, new electronic design automation (EDA) tools and techniques need to be developed based on integrating devices from emerging novel material-based technologies. The aim of this book is to explore the materials and design requirements of these emerging integrated circuit technologies, and to outline their prospective applications. It will be useful for academics and research scientists interested in future directions and developments in design, materials and applications of novel integrated circuit technologies, and for research and development professionals working at the cutting edge of integrated circuit development.
Inspec keywords: thin film transistors; integrated circuit interconnections; graphene devices; graphene; density functional theory; III-V semiconductors; high-k dielectric thin films; memristors; integrated optoelectronics; memristor circuits; boron compounds; bio-inspired materials; nanoelectronics; molybdenum compounds; wide band gap semiconductors; integrated circuit modelling; semiconductor heterojunctions; tunnel field-effect transistors; CMOS memory circuits; single electron devices; junctionless nanowire transistors
Other keywords: tunnel junctions; density functional theory; nanometer CMOS technologies; organic thin-film transistors; DFT application; optoelectronic applications; DNTT modeling; graphene materials technology; memory devices; advanced technologies; tunnel field-effect transistors; current transport models; low-dimension materials-based interlayer TFET; memristor devices; high-K dielectrics; organic-inorganic heterojunctions; molybdenum disulfide-boron nitride junctionless tunnel effect transistor; memristor-based circuits; graphene-compatible biomaterials; doping-free tunnelling transistors; single electron devices; next generation integrated circuits; interconnects
Subjects: Superconducting junction devices; Integrated optoelectronics; Semiconductor technology; Semiconductor integrated circuits; Semiconductor devices; Dielectric materials and properties; Integrated circuits; General electrical engineering topics; Molecular electronics; Resistors; Digital electronics
Graphene with its unique electronic properties is highly suitable for numerous electronic applications. Among different growth techniques, CVD is most promising due to its low cost and large area. However, growth of large-area single crystal graphene is still challenging. Owing to its zero bandgap property, graphene is not yet suitable for digital applications. However, finite bandgap can be obtained in the form of GNR which demonstrates width and edge-type dependent energy bandgap. GNR TFET can be a viable option for low power high-performance integrated circuit design. By utilizing the zero band properties of graphene, the promise of graphene interlayer tunnel transistor can also be explored. Other than graphene 2D materials such as layered transition-metal dichalcogenide (TMD) and Xenes have emerged and shown great promise for electronics, photonics, energy harvesting, and biosensors.
Biomedical materials have come a long way, from inert supportive materials to bioactive and responsive implants. Biocompatible and bioabsorbable materials have made life with implants better and manageable. Portable devices which could continuously monitor the condition of the patients by measuring vital signals and biosensing, wirelessly transmitting the data to medical practitioner who could give timely feedback and initiate therapy from remote location are nearing commercialization. The advances in nano materials and nano characterization techniques have made this feasible.
Single electron transistors are widely perceived as the next generation devices, and beyond Moore's law devices due to their promising aspects of low power consumption, high switching speed, compact size, and importantly the ability to shrink to atomic scale. The single electron devices operation is based on the quantum phenomenon called “tunneling”. Though the basic structure and operating principle of these devices is quite simpler, their fabrication and real-time operation is equally difficult, as it requires multiple conditions of Coulomb blockade to be satisfied for incoherent transport. This chapter provides comprehensive information about the single electron devices, starting from their benefit over other devices in the same series, associated concepts, operating principle, and the notable advancements in experimental as well as theoretical research on these devices. This chapter is expected to work as an absolute guide for any researcher interested in single electron devices.
In this chapter, we have shown how to use DFT for modelling material and finding their electronic structure. We have shown how to calculate the band diagram and expanded it to the calculation of transport. Hybrid material modelling has been shown in the context of VLSI interconnect. We also described the calculation methods for quantum capacitance of a hybrid G/Cu nanoribbon using DFT. Although in this chapter we have shown up to transport calculation and capacitance properties, DFT can be implemented to calculate other relevant properties of the material. This calculation methodology will help finding transport properties and quantum capacitance of emerging materials. The chapter can be a good starting point in advancing an understanding of electrical performances of other nanostructures for possible interconnect and device materials.
This chapter presents the device description, characteristics, and various applications of the memristor in analog and digital applications.
Various properties of different optimized organic solvents and graphene oxide-doped poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) films, PEDOT:PSS/Si heterojunctions, and solar cells have been studied in detail. The conductivity of PEDOT:PSS films was enhanced by three orders of magnitude with graphene oxide whereas all films remain highly transparent (>85%) in the visible region. The partial removal of PSS and the formation of conducting PEDOT-connected networks contribute to the enhanced electrical conductivity of PEDOT:PSS films. The removal of PSS was also confirmed by CAFM measurements. Solar cell fabricated with ethylene glycol-doped PEDOT:PSS film showed a maximum power conversion efficiency as compared to other solvents-doped PEDOT:PSS film. The highly conducting and transparent material can be used in various future optoelectronic devices.
The objective of this chapter is to use various electrical characterization techniques to study the interface quality and high-K dielectrics deposited by various process conditions. This provides comprehensive information on the defects, such as density, energy level, time constant and how they interact with other parameters (like flat band voltage, VFB , and dielectric lifetime). Both theoretical model and experimental work are described. Different evaluation methods can provide a good analytical approach to study the dielectrics in the gate stacks. The correlation of experimental data from different methods can enhance the understanding of the defects behavior. Since the next-generation gate dielectrics on high-mobility substrates involve nanoscale devices, it requires a detailed understanding to integrate the technology into standard CMOS technology. Furthermore, this study discusses the advantages and disadvantages of various techniques, since each method has its own limitations such as like sensitivity, range, different extracted parameters, and the difficulty of implementation.
In this chapter, novel technology and modeling of DNTT-based OTFT is presented by considering field-dependent mobility model and density of states model. Finite element method (FEM)-based device simulation model is able to produce output characteristics in linear and saturation region and transfer characteristics below and above the threshold region of a DNTT-based OTFT. Some important applications, advantages, and disadvantages of OTFTs are also discussed briefly.
As device dimensions are continuously down-scaling into sub-10 nm regimes, complementary metal-oxide semiconductor technology is facing severe challenges such as increased static power consumption, poor gate controllability, enhanced short-channel effects (SCEs), random dopant fluctuations (RDFs) and process-voltage temperature (PVT) variation, hence, conventional metal-oxide-semiconductor fieldeffect transistors (MOSFETs) have failed to be a worthy candidate for nano-electronics and micro-electronics regime. Recently, the tunnel FETs (TFET) gain tremendous attention because of their low standby power consumption and scalable subthreshold swing (SS). The TFET is a gated P-I-N diode, where ON-state current would be due to band-to-band tunnelling (BTBT) instead of thermionic emission, and they exhibit very low OFF-state current of the order of fA/mm, which makes them a potential candidate for low power consumption. The heavily doped nature of TFETs causes certain problems, and to address them, the concept of dynamically configurable doping-free (DF) TFETs was recently proposed. In this chapter, a detailed analysis of dynamically configurable TFETs such as the working principle, I-Vcharacteristics, fabrication flow and the effect of process and temperature variation is presented.
In this chapter, an analytical current transport model of a p-i-n n-type armchair GNR TFET is developed which is compared with numerical simulation. Two separate current transport models are derived analytically from semi-classical and semi-quantum modeling approaches. Non-equilibrium Green function (NEGF)-based numerical simulation study is also carried out. Results obtained from these two methods are compared with the numerical simulation to establish analytical models. The analytical model in the work of Zhang et al. [2] is revisited and results are also compared with the analytical and numerically simulated results in this work. Furthermore, GNR TFET's performance is studied for varying GNR width using semi-classical, semi-quantum and NEGF simulation-based current transport models. Finally, complementary GNR TFET inverter for digital circuit design is demonstrated through the computation of voltage transfer characteristic from all three modeling approaches.
A new type of graphene-switching transistor termed as "junctionless tunnel effect transistor (JTET)" based on graphene-hBN-graphene vertical heterostructure and interlayer tunneling is proposed and an analytical current transport model has been developed. The drain current in graphene JTET flows between the source and drain of bottom graphene layer. The current in the channel is regulated by the shift in channel Fermi level which depends on the net vertical tunneling of carriers from top graphene to bottom graphene layers through hBN. Performance of graphene JTET is evaluated for different numbers of hBN layers. A comparison between graphene JTET and ITRS projected 2020 nMOSFET is also provided apart from graphene JTET performance comparison with similar iTFETs. Current saturation is observed in graphene JTET output characteristic for both p- and n -type operations, which makes graphene JTET suitable for digital circuit design. Graphene JTET is also capable of suppressing NDR effect, and shows steep subthreshold slope with high on/off current ratio and normal operation at room temperature. A complementary vertical inverter is presented similar to a CMOS inverter and analyzed for its performance. Graphene JTET vertical inverter gives inverter gain higher than unity at the low supply voltage and both low and high noise margins. It is concluded that with an average 25 mV/decade subthreshold slope at 0.1 V supply voltage and a current ratio of ~104 , graphene interlayer junctionless tunnel effect transistor meets the ITRS requirement of device scaling for energy-efficient circuit design.
In this chapter, the operating principle of JTET discussed in Chapter 11 has been extended for the study of MoS2 JTET considering MoS2 /hBN/MoS2 for reduced subthreshold slope operation and sustainable leakage. The interlayer tunneling-based barrier control mechanism as proposed for graphene JTET in Chapter 11 and [16] is used for the current transport study of MoS2 JTET through self-consistent simulation method [22]. Similar to graphene JTET, multilayer hBN is considered as the gate dielectric for MoS2 JTET. The performances of MoS2 JTET are compared with the earlier reported graphene-based iTFET.