The demand for ever smaller and portable electronic devices has driven metal oxide semiconductor-based (CMOS) technology to its physical limit with the smallest possible feature sizes. This presents various size-related problems such as high power leakage, low-reliability, and thermal effects, and is a limit on further miniaturization. To enable even smaller electronics, various nanodevices including carbon nanotube transistors, graphene transistors, tunnel transistors and memristors (collectively called post-CMOSdevices) are emerging that could replace the traditional and ubiquitous silicon transistor. This book explores these nanoelectronics at the circuit and systems levels including modelling and design approaches and issues. Topics covered include self-healing analog and radio frequency circuits; on-chip gate delay variability measurement in scaled technology node; nanoscale finFET devices for PVT aware SRAM; data stability and write ability enhancement techniques for finFET SRAM circuits; low-leakage techniques for nanoscale CMOS circuits; thermal effects in carbon nanotube VLSI interconnects; lumped electro-thermal modeling and analysis of carbon nanotube interconnects; high-level synthesis of digital integrated circuits in the nanoscale mobile electronics era; SPICEless RTL design optimization of nanoelectronic digital integrated circuits; green on-chip inductors for threedimensional integrated circuits; 3D network-on-chips; and DNA computing. This book is essential reading for researchers, research-focused industry designers/developers, and advanced students working on next-generation electronic devices and circuits.
Inspec keywords: integrated circuit design; high level synthesis; VLSI; SRAM chips; MOSFET; CMOS integrated circuits; integrated circuit interconnections; three-dimensional integrated circuits; carbon nanotubes; radiofrequency integrated circuits; MOSFET circuits; analogue integrated circuits; circuit stability; network-on-chip; nanoelectronics; digital integrated circuits
Other keywords: TSV inductors; voltage drop; FinFET SRAM circuits; on-chip gate delay variability measurement; process variation; nanoscale FinFET devices; static random access memory chips; radio frequency ICs; scaled technology node; 3D ICs; leakage-optimal digital IC design exploration; HLS technique; SPICEless RTL design optimization; CNT; carbon nanotube VLSI interconnects; digital ICs; lumped electro-thermal modeling; leakage power dissipation; temperature variation; high-level synthesis techniques; DNA computing; 3D NoC-based nanosystem design; write ability enhancement techniques; nanoelectronic digital integrated circuits; FinFET memory design techniques; through-silicon-vias inductors; nanoscale mobile electronics; thermal effects; nanoscale analog ICs; data stability; green on-chip inductors; self-healing analog circuit; post-CMOS electronics; nano-CMOS electronics; radio frequency circuits; PVT-aware SRAM; leakage power reduction; propagation delay; nanoelectronic circuit; post-manufacturing circuit performance metrics; voltage variation
Subjects: Semiconductor integrated circuit design, layout, modelling and testing; Insulated gate field effect transistors; Network-on-chip; Analogue circuit design, modelling and testing; Metallisation and interconnection technology; Microwave integrated circuits; Digital circuit design, modelling and testing; Fullerene, nanotube and related devices; Memory circuits; Fullerenes, carbon nanotubes, and related materials (engineering materials science); Semiconductor storage; General and management topics; Network-on-chip; CMOS integrated circuits; General electrical engineering topics
Process variation is the most critical issue for the nanoscale analog and radiofrequency integrated circuits (ICs). There are many traditional techniques to mitigate the process variations problems which are mainly based on some form of static approach. However, as the traditional over-design technique becomes impractical, on-chip self-healing which is a dynamic approach has emerged as a promising methodology to address the variability issue. The key idea of self-healing is to actively monitor the post-manufacturing circuit performance metrics and then adaptively adjust a number of tuning knobs, such as bias voltage, in order to meet the given performance specifications. This chapter discusses the self-healing mechanism based analog and radio-frequency ICs.
The previous chapter focused on the process variations issue in This chapter focuses on the issue of process variations in the circuits. The chapter first presents detailed discussions of the sources ity and types of variability. Then the discussions are focused on the variations on the propagation delay of the digital integrated circuits. have been discussed thoroughly as an experimental evaluation.
This chapter describes nanoscale FinFET devices and their application in SRAM design. It also discusses variability of nanoscale integrated circuits (ICs) and introduces variability-aware memory design. In the previous two chapters, process variations were discussed for analog and digital ICs. However, this chapter focuses on futuristic memory design. A comprehensive variability including process, voltage and temperature (PVT) variations has been discussed for future SRAM design. After analysing the results of PVT-aware designs, it is found that sensitivity-driven IG-FinFET-based SRAM is the most suitable technique for reliable and high-density memories. The design of SRAM using a post-CMOS device, namely FinFET widely adopted in semiconductor industry has been specifically elaborated.
Six-transistor static random-access memory (6T SRAM) cell is the fundamental building block of memory cache in modern microprocessors. Each bit of data is stored in an individual 6T SRAM cell in the memory subsystem. Read data stability and write ability of 6T SRAM cells are degraded with the scaling of CMOS technology. Conventional circuit techniques for achieving wider voltage margins during read and write operations cause significantly larger silicon area and increased power consumption. Several alternative FinFET memory design techniques are presented in this chapter for achieving stronger data stability during read operations and wider voltage margin during write operations without causing area and power consumption overheads in the memory subsystems of microprocessors.
The previous few chapters focused on the variability issues of the nanoscale integrated circuits (ICs) for diverse applications including analog, radio frequency (RF), digital and memory ICs. The designs of such ICs are based on nanoscale bulk MOSFET and FinFET devices. The current chapter presents the leakage power dissipation which is an important issue of CMOS device in ultra-DSM regime. Leakage power dissipation is a major challenge especially for the energy efficient design of all battery-operated and portable real-time embedded systems in modern era. This chapter describes the various sources of leakage power, leakage and variability issues and provides a possible solution using some important leakage power reduction techniques at circuit/logic level for the state-of-the-art CMOS ICs.
This chapter is on the thermal effects in contrast to the process variations or leakage issues of the previous chapters. The thermal effect is considered in interconnects of the integrated circuits (ICs). In a paradigm shift, not traditional metal interconnects, but carbon nanotube (CNT) based interconnects are considered. Thus an important post-CMOS era IC design consideration, the CNT-based interconnects is presented in detail in this chapter.
Carbon nanotubes (CNTs) due to their unique electrical, thermal, and mechanical properties are being investigated as promising candidate material for on-chip and off-chip interconnects. The attractive mechanical properties of CNTs, including high Youngs modulus, resiliency, and low thermal expansion coefficient, offer great advantage for reliable and strong interconnects, and even more so for local and global on-chip interconnects. With aggressive scaling, on-chip interconnects contribute to power consumption and heat build-up due to their increasing parasitics with scaling which detriment overall energy efficiency of circuits. Due to their unique properties, CNTs present an opportunity to address these challenges and provide solutions for reliable signal and power/ground interconnects. In this chapter, we perform detailed electro-thermal analyses of horizontally aligned CNTs and report on their performance and voltage drop.
Digital integrated circuits (ICs) are the main workhorse of all modern consumer electronic systems. Digital ICs are much more complex and more closely follow the technology scaling as compared to the analog or mixed-signal ICs. For example, the transistor count can be in billions the device sizes at this point can be 14 nm FinFET in the digital ICs. However, the good news for digital ICs is that the digital designs have well-defined abstractions including system, architecture, logic. This Chapter is focused at the architecture level of the digital ICs. In particular, detailed discussions of high-level synthesis technique has been presented that can generate digital ICs. Trust of electronic systems that are used in day-to-day life is critical. This Chapter also discusses the HLS technique that can generate trusted digital ICs.
The previous chapter discussed various steps of high-level synthesis (HLS) which are used for design exploration of digital integrated circuits. It then discussed specific methods for dynamic power dissipation optimization as well as synthesis of hardware-trojan free digital integrated circuits. The methods relied on various bio-inspired algorithms for design space exploration. As complementary material of the previous chapter, this chapter presents HLS methods for leakage-optimal digital integrated circuit design exploration. Specifically, a paradigm shift approach is presented in which the complete HLS flow is performed without use of any electronic design automation (EDA) tool. All the associated tasks such as modeling, characterization, and optimization are performed using non-EDA tools, and hence this is called the “SPICEless” approach. For a specific objective of nanoelectronic digital integrated circuits, gate-leakage power dissipation is targeted.
This chapter deals with a completely different aspect of circuit and design as compared to the previous chapters. This chapter discusses three-dimensional integrated circuits (3D ICs) as compared to the planner integrated circuits of the previous chapters. The 3D ICs have shown significant promise for the future post-CMOS era circuits and systems to build high-performance systems with minimal silicon foot print. This chapter specifically discusses practical approaches to through-silicon-via (TSV) inductors which constitute the vertical signal, power and thermal paths which is very critical for 3D ICs.
Four primary aspects of chip design are processor, memory, IO, and communication. Communication amalgamated over a SoC (system-on-chip) is the basis of origin of an NoC (network-on-chip). Continuous increase in processing/communication needs with the rapid growth in VLSI industry providing higher and higher integration density within a single die has boosted the step towards this new paradigm shift by the researchers. Advent of three-dimensional (3D) integrated circuits (ICs) design technologies has given this direction another positive thrust. Researchers are indeed very hopeful with the amalgamation of these two different technologies and thereby in developing new methodologies for designing 3D NoCs to cater the need of high-performance nanoscale computing and communication systems tomorrow. This chapter describes different design challenges, available technologies, design and performance issues and parametric measurement of such nanoscale systems, emerging cutting-edge technologies, and possible future directions in designing 3D NoC-based nanosystems.
With rapid growth in very-large-scale integration technology following Moore's law, the integration density of transistors has reached billions. This caused scaling of transistors to reach deep submicron regime resulting in failure of classical physics. Eventually, classical computing technologies have reached a physical limit and caused slowing down of Moore's law. Also, current leakage becomes a major problem in classical technology at such small size that heats up the chip. So Dennard scaling, which states about the constant power density with the decrease of transistor size also failed. It caused the switch to multi-core technology but that too seems to be at the end due to Dark Silicon issues. As a plausible alternative, researchers are trying to switch to some non-Complementary Metal-Oxide Semiconductor (CMOS) technology, e.g., quantum computing, bio-inspired computing such as deoxyribonucleic acid (DNA), etc. Besides mitigating the concerns faced in conventional technology, DNA computing comes with a bunch of other benefits too to cater the needs of future-generations computing, viz. massively parallel operations, huge information density over silicon, etc. In this chapter, with an introduction to structure of DNA and how DNA computing works, several fields of DNA computing have been explored followed by how DNA computing can be applied to solve several problems otherwise known as hard on conventional computer with some comments on possible future research directions in this promising field.
