Nano-CMOS and Post-CMOS Electronics: Devices and Modelling
2: Division of Electrical & Computer Engineering, Louisiana State University, Baton Rouge, Louisiana, USA
The demand for ever smaller and portable electronic devices has driven metal oxide semiconductor-based (CMOS) technology to its physical limit with the smallest possible feature sizes. This presents various size-related problems such as high power leakage, low-reliability, and thermal effects, and is a limit on further miniaturization. To enable even smaller electronics, various nanodevices including carbon nanotube transistors, graphene transistors, tunnel transistors and memristors (collectively called post-CMOS devices) are emerging that could replace the traditional and ubiquitous silicon transistor. This book explores these nanoelectronics at the device level including modelling and design. Topics covered include high-k dielectrics; high mobility n and p channels on gallium arsenide and silicon substrates using interfacial misfit dislocation arrays; anodic metal-insulator-metal (MIM) capacitors; graphene transistors; junction and doping free transistors; nanoscale gigh-k/metal-gate CMOS and FinFET based logic libraries; multiple-independent-gate nanowire transistors; carbon nanotubes for efficient power delivery; timing driven buffer insertion for carbon nanotube interconnects; memristor modeling; and neuromorphic devices and circuits. This book is essential reading for researchers, research-focused industry designers/developers, and advanced students working on next-generation electronic devices and circuits.
Inspec keywords: system-on-chip; integrated circuit interconnections; III-V semiconductors; thin film devices; memristors; digital integrated circuits; CMOS logic circuits; integrated circuit reliability; integrated circuit modelling; hafnium compounds; statistical analysis; nanoelectronics; MIM devices; dislocation arrays; gallium arsenide; field effect transistors; carbon nanotubes; neural chips; high-k dielectric thin films; graphene devices; titanium compounds; capacitors
Other keywords: nanoscale devices; timing driven buffer insertion; device reliability; MIM capacitors; material level solution; Si; HfO2; metal interconnects; GaAs; CNTs; electrical properties; interfacial misfit dislocation arrays; nanoelectronics; high mobility p-channels; nanostructured anodic high-κ dielectrics; reliable power delivery networks; memristor modeling-static methodology; future generation integrated circuits; multiple-independent-gate field-effect transistor; statistical methodology; compound semiconductors; multiple-independent-gate nanowire transistors; TiO2; MIGFET; junction transistors; digital integrated circuits; high mobility n-channels; high-speed high-performance interconnect; 2D integrated circuits; FinFET based logic libraries; graphene transistors; post-CMOS electronics; advanced SoC design; doping-free transistors; nano-CMOS electronics; carbon nanotube interconnects; thin film device; neuromorphic devices; FinFET-based processors; memristor-based efficient neuromorphic realizations; stochastic methodology; on-chip capacitors; anodic metal-insulator-metal capacitors; technology scaling; neuromorphic circuits; metal-gate CMOS based logic libraries; logic libraries; next-generation processors; 3D integrated circuits; passive element
Subjects: Reliability; Dielectric materials and properties; Logic circuits; Fullerene, nanotube and related devices; Probability and statistics; General and management topics; System-on-chip; General electrical engineering topics; Neural net devices; Capacitors; Metallisation and interconnection technology; Fullerenes, carbon nanotubes, and related materials (engineering materials science); Thin film circuits; CMOS integrated circuits; Probability and statistics; Resistors; Insulated gate field effect transistors; System-on-chip; Semiconductor integrated circuit design, layout, modelling and testing; Neural nets (circuit implementations)
- Book DOI: 10.1049/PBCS029E
- Chapter DOI: 10.1049/PBCS029E
- ISBN: 9781849199971
- e-ISBN: 9781849199988
- Format: PDF
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Front Matter
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1 High-κ dielectrics and device reliability
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Technology scaling continues to be driven by the cost per function due to proliferation of mobile computing. With sub-45-nm technology node, high-κ gate dielectrics such as HfO2 have emerged. This chapter is dedicated to high-κ dielectrics with particular emphasis to most important characteristics the reliability.
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2 High mobility n and p channels on gallium arsenide and silicon substrates using interfacial misfit dislocation arrays
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3 Anodic metal-insulator-metal (MIM) capacitors
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Metal-insulator-metal (MIM) capacitor is an important passive component in RF, analog and mixed signal (RF-AMS) circuits. It takes a large circuit area of integrated circuits (ICs) compared to other passive and active components. So miniaturization of MIM capacitors, along with transistors, has become essential in design and fabrication of future ICs. This has made a trend to design high capacitance density MIM capacitors with novel dielectric materials. In this regard, many works were carried out in fabrication of various nanostructured high-k dielectric MIM capacitors over the last decade. However, many of them suffered with structural defects, interface traps, and poor polarization process due to limitations of fabrication processes. The anodization process is an electrochemical oxidation of metals which had been demonstrated for the preparation of high-k dielectrics with improved crystalline properties, low structural defects, and improved ionic polarization. In this chapter, the fabrication and characterization of nanostructured anodic high-k MIM capacitors are presented. Many of these capacitors are meeting the requirements of International Technology Roadmap for Semiconductor with crystalline properties and improved ionic polarization.
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4 Graphene transistors - present and beyond
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Graphene is being explored as a material to build scaled transistors for high speed operations (e.g., 10s of GHz) of integrated circuits. This chapter discusses the state-of-art of the graphene-based transistors with a prediction for its future directions.
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5 Junction and doping-free transistors for future computing
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Continued down-scaling of device dimensions poses severe challenges and difficulties for complementary metal-oxide semiconductor technology, particularly fabrication complexities, process variability, and short channel effects. These challenges mainly arise due to abrupt doping profile requirement at junctions and random dopant fluctuations (RDFs). Recently, the junctionless field-effect transistors (JLFETs), also known as gated resistors, have widely attracted attention, as they do not require formation of any metallurgical junctions (P-N, N+-N, or P+-P) and doping concentration gradient throughout the device. Thus, they relax abrupt doping profile requirements and greatly simplify the fabrication process. A key requirement for JLFETs is the formation of a semiconductor layer that should be thin and narrow enough to be depleted when the JLFET is in off-state. At the same time, semiconductor layer should be doped enough to achieve an adequate amount of drain current in on-state. Therefore, JLFETs are generally made of heavily doped silicon nanowires. The heavily doped nature of JLFETs causes certain problems, and to address them, the concept of doping-free (dopingless) JLFETs was recently proposed. In this chapter, detail study of both junction-free and doping-free transistors are presented based on 2-D device simulation with model calibrated to experimental data.
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6 Nanoscale high-κ/metal-gate CMOS and FinFET based logic libraries
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During the last four decades, VLSI technology growth has been driven by miniaturization that reduces cost per transistor, power consumption per transistor, with higher packing density and reduced cost of operation. However, the small transistor size leads to very high electric fields across the gate oxide which causes the difficult problem of gate-oxide leakage. This problem is mitigated by high-κ/ metal-gate (HKMG) technology, in which the gate material is copper (going back to metal from polysilicon), and the gate-oxide material is not silicon dioxide. At the same time, explosive growth of mobile portable electronics has been the driver for many scientific, engineering, and technological breakthroughs in the last few decades. Mobile electronics in particular, such as smart mobile phones, spend most of their operational time in waiting for a call or similar event. However, during these wait states, leakage power dissipation has been a major issue since it drains the battery continuously. The industry has explored various solutions to reduce the OFF-state leakage and multiple gate devices emerged as a solution to this problem. Double-gate FinFET technology is considered as a solution to reduce OFF-state leakage while having faster ON and OFF transitions and low-power (LP) dissipation. This chapter discusses these devices and presents logic libraries which can be used in the digital synthesis of large integrated circuits using such devices through electronic design automation (EDA) tools.
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7 FinFET and reliability considerations of next-generation processors
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Recent experimental studies reveal that Fin field-effect-transistor (FinFET) devices commercialized in recent years tend to suffer from more severe negative bias temperature instability (NBTI) degradation compared to planar transistors, necessitating effective techniques on processors built with FinFET for endurable operations. We propose to address this problem by exploiting the device heterogeneity and leveraging the slower NBTI aging rate manifested on the planar devices. We focus on modern graphics processing units in this study due to their wide usage in the current community. We validate the effectiveness of the technique by applying it to the warp scheduler and L2 cache, and demonstrate that NBTI degradation is considerably alleviated with slight performance overhead.
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8 Multiple-independent-gate nanowire transistors: from technology to advanced SoC design
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The focus of this chapter is a novel class of devices such as Multiple-Independent-Gate Field-Effect Transistor (MIGFET) which can provide better functionality and flexibility as compared to classic Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). Specific emphasis is given to Three-Independent-Gate Field-Effect Transistor (TIGFET).
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9 Exploration of carbon nanotubes for efficient power delivery
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Carbon nanotubes (CNTs) due to their unique mechanical, thermal, and electrical properties are being investigated as promising candidate material for on-chip and off-chip interconnects. The attractive mechanical properties of CNTs, including high Young's modulus, resiliency, and low thermal expansion coefficient offer great advantage for reliable and strong interconnects, and even more so for three-dimensional (3D) integration. Through-silicon-vias (TSVs) enable 3D integration and implementation of denser, faster, and heterogeneous circuits, which also lead to excessive power densities and elevated temperatures. Due to their unique properties, CNTs present an opportunity to address these challenges and provide solutions for reliable power delivery networks in two-dimensional (2D) and 3D integration. In this chapter, we perform detailed analyses of horizontally aligned CNTs and report on their efficiency to be exploited for both 2D and 3D power delivery networks.
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10 Timing driven buffer insertion for carbon nanotube interconnects
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In the nanoscale technology, both the device and interconnect performances affect the overall performance of the integrated circuits and systems in which they are used. So, it is quite natural to explore various solutions for devices as well as interconnects to mitigate the challenges of technology scaling and meet high-speed demand. This chapter discusses the use of carbon nanotubes (CNTs) as a potential high-speed high-performance interconnect as compared to the metal interconnects.
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11 Memristor modeling - static, statistical, and stochastic methodologies
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12 Neuromorphic devices and circuits
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Over the past few decades, significant strides were made in understanding the processes in the brain and mapping these processes onto different computing substrates for efficient information processing. Neuromorphic researchers strive to abstract the functional and structural behavior of the mammalian brain onto custom hardware platforms with various degrees of complexity. To this end, memristor device technology has enabled efficient neuromorphic realizations owing to its nonvolatility, multiple conductance states, and small footprint. In this chapter, a comprehensive overview of the memristor devices and their role in designing neuromorphic circuit primitives will be presented.
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Back Matter
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