This book brings together the leading researchers, in high frequency analogue filters to highlight recent advances and identify promising directions for future development.
Inspec keywords: circuit tuning; switched current circuits; switched filters; active filters; low-power electronics; adaptive filters; analogue circuits; operational amplifiers; MOSFET
Other keywords: on-chip automatic tuning; switched-current filter; high frequency integrated analogue filter; operational transconductance amplifier; low voltage technique; log domain filter; MOSFET-C technique; gm-C filter; analogue adaptive filter; active filter; integrated inductor
Subjects: Filters and other networks; Time varying and switched networks; Analogue processing circuits; Analogue circuit design, modelling and testing; Insulated gate field effect transistors; Amplifiers
This chapter has addressed some topics in gm-C filter design. Two integrator loop, LC ladder-based and multiple loop feedback OTA-C filter structures have been studied. Design examples using a wideband high output resistance OTA have been presented. Current-mode gm-C filters have been discussed and compared with voltage-mode counterparts. Tuning issues including both analogue and digital schemes have been discussed.
The MOSFET-C method for fully integrated filters is a mature and proven design technique. Over the last 14 years, it has been used in high dynamic-range, continuous-time, large-volume applications at low and medium frequencies, and recently at frequencies above 100 MHz. The traditional strength of this method has been its capabilities for best power efficiency and best dynamic-range realisations among all integrated continuous-time filters. Conventional and new theoretical support explaining this performance has been presented in detail. The next generation MOSFET-C filters will cover increasingly higher frequencies. Clear experimental and theoretical evidence shows that an extension of this technique to frequencies approaching 1 GHz is within reach. The crucial IC technology advancement enabling this development is the advent of very high speed, inexpensive BiCMOS. The MOSFET-C method is ideally suited for this technology. It uses MOS transistors for obtaining tuned analogue cells with the largest possible on-chip dynamic range for a given power dissipation, and bipolar transistors for obtaining amplifiers with the largest possible on-chip gain-bandwidth product.
The advent of highly integrated wireless transceivers is a platform for the research and development of active LC filters on silicon chips. The design of such filters presents great challenges to designers. The quality of on-chip reactive components is the main reason for this, since the losses and the parasitics in those components can result in frequency response distortion, and the need for active components, like negative resistors, limits dynamic range. Nevertheless, the performance already achievable may be sufficient for the implementation of such filters in certain parts of the transmitter, e.g. at the output of mixers, where a large signal must be bandpass-filtered. Many improvements are needed, and can be expected in the future, in the realisation of higher quality on-chip inductors and capacitors, in filter synthesis when the reactive component losses are large, in the accurate compensation of such losses using negative resistances, in the implementation of those resistances with low noise and high linearity, and in the automatic tuning of on-chip active LC filters.
Log domain filtering is a very new area of active filter design. As a result, there are no generally accepted design procedures. The discussion in this chapter has therefore centred on familiarising the reader with the basic ideas and concepts related to this new idea. An attempt has been made to summarise several perspectives on the design of these filters, with the intent to give the reader an ability to not only appreciate how to go about designing log domain filters, but also access the literature for more information and perspective.
We have established a viable approach for low voltage filters using the switched current technique. First, we showed that switched currents, unlike switched capacitors, suffer no performance degradation as the supply voltage is lowered. When the supply reaches about IV, class AB switched currents can be expected to outperform switched capacitors.
In this chapter, to improve the reliability and cost of signal processing electronics, entire systems must be integrated on to a single chip. In many applications, an all-digital or all-analogue system is impossible because both analogue and digital external interfaces are required. So we must assume that both analogue and digital circuits will have to coexist on the same IC. The advance of digital process technologies will enable faster digital signal processing with a smaller integrated circuit area and lower power consumption. At the same time it will become increasingly difficult to implement accurate and linear analogue circuits. Therefore, analogue adaptive filters are likely to continue to be targeted at applications where they can simplify or reduce the analogue circuitry required elsewhere on the chip.
We have in this chapter presented the main ideas that have been proposed in the literature for the tuning of integrated continuous-time filters. To minimise interference problems, master-slave schemes are used most often. Although first-order master stages have been employed, typically, second-order filters or oscillators are used because they can be matched more reliably to second-order slave filter stages. Even for that case, matching of much better than 1 percent between master and slaves on a chip is difficult to maintain. This problem increases at higher frequencies when parasitic components become more important. Whether the master-slave technique or a direct tuning method is used in cases where the filter has periodic inactive periods, it is helpful for better matching and tracking that a filter architecture is chosen that has many identical circuit blocks. The tuning algorithm will be simpler and the control circuitry smaller, less noisy and less power-hungry DFT is a well understood and accepted requirement in integrated circuits, i.e. an IC is 'designed for test'. Analogously, it is crucial for success that an integrated analogue filter is 'designed for tuning'. The filter topologies must be tunable, must be insensitive to parasitics, and be constructed with well matched circuit blocks. The unavoidable overhead penalty for tuning will then be minimised.
