A comprehensive introduction and reference for all aspects of IC testing, this book includes all of the basic concepts and theories necessary for advanced students, from practical test strategies and industrial practice, to the economic and managerial aspects of testing.
Inspec keywords: integrated circuit testing; VLSI; signal processing; mixed analogue-digital integrated circuits
Other keywords: VLSI testing; mixed analogue/digital IC; mixed analogue/digital techniques; digital network testing; integrated circuit testing; signal processing; IC chip; IC testing
Subjects: Signal processing and detection; Mixed analogue-digital circuits; Integrated circuits; Semiconductor integrated circuits; Semiconductor integrated circuit design, layout, modelling and testing; Analogue circuit design, modelling and testing; Signal processing and conditioning equipment and techniques
This chapter is a broad overview of the problems of testing circuits of VLSI complexity and systems into which they may be assembled. As will be appreciated, the testing problem is not usually one of fundamental technical difficulty, but much more one of the time and/or the cost necessary to undertake a procedure which would guarantee 100% correct functionality. The subsequent chapters of this text will therefore consider the types of failures which may be encountered in microelectronic circuits, fault models for digital circuits, the problems of observability and controllability and the various techniques that are available to ease the testing of both digital and mixed analogue/digital circuits. Finally, the financial aspects of testing which reflect back upon the initial design of the circuit or system will be considered, as well as the production quantities that may be involved. We will conclude this chapter with a list of publications which may be relevant for further general or specific reading. The more specialised ones may be referenced again in the following chapters.
In considering the techniques that may be used for digital circuit testing, two distinct philosophies may be found, namely: (a) to undertake a series of functional tests and check for the correct (fault free) 0 or 1 output response(s); (b) to consider the possible faults that may occur within the circuit, and then to apply a series of tests which are specifically formulated to check whether each of these faults is present or not.
This chapter considers several strategies for generating tests for digital circuits which, with the noticeable exception of I DDQ testing involve the monitoring of the 0 and 1 primary output response to appropriate input test vectors. By far the greatest development effort has been concerned with combinational logic. Roth's D-algorithm forms the basis of many automatic test pattern generation programs, but the computational effort in producing ATPG programs for the increasing size and complexity of present-day VLSI circuits is becoming prohibitive. This has forced an increasing interest in other means of test pattern generation, which usually involves some partitioning of the circuit at the design stage so as to allow exhaustive, non exhaustive or pseudorandom test patterns to be used.
In this chapter we will consider means which have been proposed to ease the task of checking the output response when under test, so that the very large number of individual 0 or 1 output bits do not have to be compared step by step against the expected (fault-free) response. Again we shall largely be considering combinational circuits rather than sequential, the latter still requiring their own special testing consideration. Some of the concepts that we will review in this chapter have yet to be reflected in common practice, but all are part of the whole research and development effort which has taken place and still continues on testing strategies.
Because of the difficulties or complexities encountered when formulating acceptable tests for integrated circuits as they become larger and more complex, it is now essential to consider testing at the design stage of a VLSI circuit or system using VLSI parts, and not as an afterthought once the design has been completed. The old-fashioned separation between a design engineer who designs a circuit or system and a test engineer in a separate office who takes the design and then attempts to formulate an acceptable test strategy for it is no longer viable. Design for testability, sometimes called design for test and almost always abbreviated to DFT, is therefore the philosophy of considering at the design stage how the circuit or system shall be tested, rather than leaving it as a tack on exercise at the end of the design phase.
In this chapter we will consider particular circuits and circuit architectures, and how they may be tested. The fundamental principles of digital logic testing will still be relevant, but specific fault mechanisms, circuit failures and/or testing procedures may now be involved. Additionally, many of the required test procedures will have been considered in detail by the IC manufacture (vendor), and therefore the OEM will not have the problem of formulating tests for such circuits from scratch as may be necessary with a system assembly of simpler ICs or other components-the problem of accessibility of the I/Os of such circuits for test purposes in a completed system assembly will, of course, still be present.
This chapter has ranged rather summarily over the testing requirements of autonomous analogue-only circuits and A-to-D and D-to-A converters, the vast majority of which will be off the shelf standard parts or standard designs. The difficulty is the very wide diversity of circuits and applications involved, see Figure 7.5, and the detailed specialist knowledge of analogue circuit design which is necessary to discuss the specification, the design and the tolerancing of most circuits in any depth. Also, all analogue circuits have an acceptable tolerance of performance in the time and frequency domain which must be part of the testing specification for the circuit, and hence simple deterministic go/no-go tests are difficult to formulate.As we have seen, functional testing of such circuits is the norm, using commercial instrumentation to generate test inputs and monitor test response. The vendor will inevitably be highly involved in the production testing of standard parts, using considerable resources and in-house expertise; the OEM will generally be involved in less comprehensive functional tests of individual components or parts.
In this chapter uncertainty in the practice of mixed-signal VLSI testing is discussed. In spite of considerable efforts from the mid 1980s onwards, when mixed-signal ICs began to grow from manageable MSI size towards LSI and VLSI complexities, the subject still remains one of continuing development in both design techniques and testing strategies and, most importantly, in appropriate hardware and software CAD resources to assist in this area. Mixed-signal design for testability is therefore still considered to be the most challenging area of present-day microelectronic circuit and system design.
The overall importance of costing does not need emphasising, since it is the responsibility of every vendor and OEM not to make a financial loss across their range of products. Microelectronic costs, however, may be difficult to assess, and may be based upon previous experience rather than on precise financial data relating to a new product. Within the theme of this text, namely testing, it would clearly be cheaper for an IC vendor not to test production wafers and finished ICs, and for an OEM not to test a final product; on the other hand it is clearly equally unacceptable to subject every manufactured product to lengthy exhaustive life tests.
The following gives the primitive polynomials with the least number of terms which may be used to generate an autonomous maximum length pseudo random sequence (an M-sequence) from an n-stage linear feedback shift register (LFSR). Alternatives are possible in many cases, particularly as n increases. Recall from Chapter 3 that the primitive polynomial has the form: 1 + a1x1 + a2x2 ... anxn.
The following gives the positions in n-stage autonomous cellular automata of the type 150 cells necessary to produce a maximum-length sequence of 2n - 1 states. All remaining cells in the n-stage string of cells are the simpler type 90 cells.
In Chapter 1 it was shown that the defect level, DL, after test was given by the theoretical relationship DL={1 - Y(1 - FC)} x 100 %. Both the 'goodness' of the fabrication process, the yield, Y, and the effectiveness of the testing procedure, FC, are involved in this result. Modelling of the number of good die on a wafer, which is principally dependent upon die size and process goodness and not upon circuit complexity, has been extensively studied, since with accurate modelling the yield, and hence the cost, of new circuits may be forecast. Also, once the detailed modelling parameters have been determined, the quality of the production lines can be maintained and possibly improved. However, the available modelling theory and available parameter values usually lag the latest production process, and as a result the yield of most production lines has historically tended to be higher than that predicted by modelling theory. (This is also true of reliability predictions for most products, where actual reliability, except for catastrophic occurrences, tends to be somewhat higher than predicted).