A wide-ranging book on the subject of mixed analogue digital ASICs, this title covers processing technology, circuit techniques and building blocks, design and applications, and CAD and supporting tools.
Inspec keywords: analogue-digital conversion; high level synthesis; switched capacitor filters; application specific integrated circuits; BiCMOS digital integrated circuits; circuit testing; BiCMOS analogue integrated circuits; operational amplifiers; video communication; signal processing
Other keywords: high level simulation; design tools; self-callibrating converters; circuit technique; automated analogue design; video communication application; algorithmic converters; hardware description languages; automated high level synthesis; switched current technique; analogue sampled data signal processing; circuit level/gate level mixed-mode simulation; high flexibility BiCMOS standard cell library; mixed analogue-digital design; data converters; mixed analogue-digital ASIC; operational amplifiers; mixed signal ASIC; advanced BiCMOS ASIC process; data conversation; switched capacitor filters; mixed analogue-digital circuit testing; oversampling converters; comparators
Subjects: Television and video equipment, systems and applications; Semiconductor integrated circuits; Telecommunication applications; Signal processing and detection; Signal processing and conditioning equipment and techniques; Mixed analogue-digital circuits; General circuit analysis and synthesis methods; Time varying and switched networks
This chapter discusses the analogue-digital converters and ASIC design.
This chapter describes LSI Logic's analogue BiCMOS technology and attempts to highlight the importance of modelling and simulation at all stages of chip manufacture and development in particular, process and device modelling are discussed as ways to improve the overall manufacturing process of a designed circuit. At its lowest level this means modelling the manufacturing steps to enable a more stable process to be developed and manufactured, whilst at its highest level it means statistically modelling the single transistor performance to enable the reliable prediction of circuit performance.
In this chapter, CMOS comparator structures have been discussed. It is shown that an OTA can only be used for low frequency applications. If a fast response time is required, latched comparators must be employed. It is shown that the resolution of a latched comparator is a function of the clock feed-through and the transistor mismatches. To overcome those problems the advantages of the OTA-latch structure are analyzed. The effect of clock feed-through and transistor mismatch can now be reduced by increasing Gm. This can best be achieved by designing the input stage at the boundary of strong inversion (Vgs-Vt ≈ 200mV). As a result the accuracy of the comparator is reduced approximately to the offset voltage of a differential pair. The speed of this comparator is approximately equal to a loaded inverter. Hence accurate high speed comparators can be obtained.
Switched capacitor filters have now been around for a decade and many powerful and sophisticated design techniques have been developed. In view of the excellent literature on this subject to which the reader may refer, the present chapter has the rather specific aim of presenting some advances developed by the authors which have made a contribution towards extending the limits for switched capacitor filters beyond the generally accepted performance boundaries shown in Figure 4.1. The areas of performance improvement considered include performance precision, maximum achievable Q-factor and maximum operating frequency.
In this chapter we introduce the switched-current technique and show how it can be used to implement various analogue sampled-data signal processing functions. The sources of error in the basic cells are identified and a number of enhanced cells, which overcome some of these errors, are described. Finally some future potential areas of application are explored.
In this chapter, after an initial discussion of the basic static and dynamic parameters which characterise data converters, conventional conversion approaches and specific techniques used in CMOS technology are described. Non-conventional and more advanced solutions are considered in two successive chapters.
This chapter discusses that the important effect of oversampling is that the power of the error associated with the quantization (quantization noise) is spread over a band that is much wider than the band of interest. Thus the digital output of an over sampled A/D converter contains a given fraction of the quantization noise that is pushed out of the band of interest. This fraction can be filtered out without affecting the informative content associated with the input signal. After filtering, the power of the quantization noise is reduced and, in turn, the resolution of the converter is increased.
This chapter described a number of data conversion circuit techniques, both for A/D and D/A, which can be employed in a wide variety of system applications which may need conversion speeds up to the order of several hundreds of kHz, or even few MHz, and conversion resolutions ranging from 8-bit to 16-bit. Firstly, we presented one of the most popular architectures for realising A/D converters with conversion resolution from 10-bits to 16-bits and conversion speeds between the audio and the video frequency bands and which is based on the well known combination of the successive approximation algorithm together with self-calibrating techniques. Then, we described a low-cost quasi-passive D/A converter yielding up to 8-bit resolution and conversion speeds up to a few MHz, and a capacitance-ratio-independent D/A converter which can achieve high conversion resolutions using operational amplifiers with relatively modest values of the DC gain. Both types of converters can be easily programmed by digital means to achieve different conversion characteristics, both for speed and resolution. Finally, we considered an algorithmic D/A converter with a built-in filtering function to shape the resulting output analogue signals, as required in a complete mixed-signal digital-to-analogue interface system. Various examples of a CMOS integrated circuit implementation were also presented to illustrate the circuit design techniques described for the self-calibrated and algorithmic converters.
The STKM2000 library is a comprehensive library arrived at from a merger between bipolar and CMOS technologies, between analogue and digital functions and between various CAD and design concepts. This merged library is able to respond to the needs of systems between sensors and actuators; from low frequencies to video frequencies; from 2.7V to 11V applications. The availability of accurate functions which combine the ability to fabricate 10K gates together with many analogue functions opens the door towards the one chip solution to many requirements in equipment design. Its availability on a majority of standard workstations with a “friendly” human interface and design manager allows any system designer to undertake the design of a mixed analogue/digital custom circuit.
This chapter has presented methods to improve element matching for MOS integrated circuits. A high degree of matching is required if a good yield is to be guaranteed in production. Methods to reduce the coupling of noise from the substrate and power supplies have also been presented. Hopefully the reader has been made aware of some of the practical aspects of mixed analogue and digital design. He should now be motivated to consider such problems for himself.
This chapter has given brief descriptions of several mixed analogue-digital chips from various segments of the market. It has also considered cases studies of four such chips from the telecommunications and automotive application areas. As stated earlier mixed signal chips are aimed at most segments of the market and as the art of designing these systems develops, the reader find many more examples appearing in the technical literature.
This chapter has outlined the incorporation of both analogue and digital circuits in a single chip to meet stringent technical and economic requirements of a video communications application. Such a hybrid approach is becoming very important for many applications in the telecommunications area, such as modems, radio-telephones and ISDN equipment in general. To obtain the maximum benefit from this approach, analogue and digital parts can not be synthesised and analysed separately but a unified approach will be found to be the best. This will result in the development of many specific mixed mode techniques in the future.
There is a very strong requirement for high level mixed-signal simulation in the design of complex mixed-signal ASICs, for design verification, design analysis and system level modelling. The key issues in such simulations are high level analogue modelling, and compatibility between analogue and digital simulation. The two main alternative approaches are to link together a circuit simulator and a logic simulator, providing some method of high level analogue modelling in the circuit simulator, or to develop high level event-driven models of analogue functions in the context of a digital simulator. There are advantages and disadvantages to each approach.
In this chapter, the principles on which mixed-mode circuit-level/logic-level simulation is based have been described. The principal areas of new development concern the interfaces between circuit-level and logic devices, in particular, the mapping of signals across those interfaces and the loads reflected onto analogue nodes by logic devices. The feasibility of mixed-mode simulation has been demonstrated by example and questions of precision and cost of simulation addressed.
With the recent improvements in processing technology which have made available reliable CMOS and BiCMOS realizations of both digital and analogue circuit components on the same chip, there has been a large increase in the number of mixed-mode circuits manufactured. The details of the processes and design techniques have been described earlier in this book. The majority of the circuits being realized are designed for specific functions and are manufactured in relatively small quantities, and hence fall under the category of application specific integrated circuits (ASICs). The increase in access to the processing lines via the silicon broker system, with the resulting decrease in price, has widened the availability of these mixed mode ASICs to many more engineers, both in industry and academia. It is expected that this trend will increase in the coming years, with about a 3-fold increase in manufacture of these circuits predicted over the next five years.
This chapter has described an advanced computer assisted design environment which employs high-level symbolic tools capable of analysing and supporting the synthesis of system architectures defined in terms of specific functional building blocks as well as the architectures of such functional building blocks defined in terms of circuit components. It has presented the general organization of a design environment, including a brief discussion of the strategy for multi-level communication and flow of information which was adopted in order to efficiently integrate such tools and thus provide high flexibility for designing mixed analogue-digital ASICs. We have also introduced the concept of synthesisers which employ a coherent, common framework for the synthesis and analysis of networks implementing different functions, each of which can also be realised using multiple topologies. Essential to such multi-function multi-topology synthesisers is the capability of automatically generating symbolic transfer functions from a given circuit description, and which was also addressed for the case of z-domain transfer functions generated from SFG's representing the operation of SC networks. Finally, we presented a knowledge-based system for designing at the architecture level SC filters based on multiple methodologies, and gave a detailed example corresponding to the methodology based on the cascade of SC biquads.
This chapter considers a flexible framework for the automatic synthesis of data conversion architectures employing binary-weighted C-arrays which can meet a broad range of input specifications, both for A/D and D/A conversion, and perform to a high degree of precision even when considering the non-idealities of the circuit components such as offset, charge injection, noise and component mismatch errors. This included not only the description of the complete architecture design and verification automation processes but also the discussion of an efficient top-down flow of design information to access a variety of lower level design environments including cell libraries, parametrized circuit module generators and circuit level compilers. By ensuring such design flexibility at the lower level, this framework also renders it easier to meet even the stringent specifications for implementation of a data conversion system employing binary-weighted C-arrays.
CAD tools for analogue (and mixed analogue-digital) circuits are receiving a great deal of attention from both research institutes and companies. Among these tools, a strong commitment is made towards developing practical silicon compilers that can be embedded into existing commercial frameworks. Present compilers are restricted from the viewpoints of design style, architecture and application, although there is an emerging generation which fits better into the structure of software environments.
