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Radar Synchronizers

Radar Synchronizers

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Synchronizers may differ substantially in systems, each producing the unique set of triggers and gates for the radar's purpose and design, and by the hardware available at the time of manufacture. Some fundamental design concepts applicable to many synchronizers will be discussed in this chapter, and one synchronizer necessary for the ASR-9 MTD system will be introduced to illustrate a more complex application. Figure 9-1 is a simple diagram of some basic timing signals required of an early ASR radar. Triggers and gates for use throughout the radar system may be produced by the synchronizer, or by other units which rely upon the synchronizer for timing triggers. Among the various timing signals are the transmitter triggers, the coho gate in magnetron systems, stc triggers, display triggers, live-time gates to enable the receiver outputs for 741 μs (for 60-mile ASR radars) or 2,471 μs (for 200-mile ARSR radars), deadtime triggers to initiate built-in-test (BIT) functions, and many others. Satisfactory operation of the MTI system places stringent requirements on the synchronizer design and stability that would not otherwise be necessary. In sophisticated tracking and range/elevation/azimuth three-dimensional systems, timing becomes so complex, and subjected to so many variables, that only a computer with several interrupts and complex subroutines can suffice.

Chapter Contents:

  • Introduction
  • The Master Trigger Blocking Oscillator
  • The Automatic Temporal Control
  • Regulation by Phantastron
  • The Circulating Trigger Loop
  • Digital MTI and Elimination of the Delay Line
  • Analog-to-Digital Conversion of the Bipolar Video
  • Basic Timing
  • Range-Cell Clock Rate
  • Timing Events Within the Range Cell
  • Timing Circuitry Block Diagram
  • Range Cells versus Shift Register Stages
  • Range Cell and Trigger Synchronization
  • The Basic Unstaggered fp Generator
  • fp Adjustment
  • Staggered fp
  • Digital Timing in Magnetron Systems
  • MTD System Timing
  • Preface and Introduction
  • Azimuth Data and the Synchronizer
  • The Coherent Processing Interval Pair (CPIP)
  • The Single-Board Computer
  • Computer Hardware
  • Brief Description of Computer Components
  • Program Counter
  • Basic Input/Output System (BIOS)
  • Nonvolatile RAM (NVRAM)
  • Instruction Repertoire
  • Program Execution
  • Interrupts
  • Interrupt Priorities
  • Status Registers
  • Interrupt Tabling
  • Watchdog Timer
  • The ASR-9 Timing Scheme
  • CPIP Azimuth
  • The MTD Front End
  • CPIP and fp Stagger
  • Complexities Introduced by the CPIP Process
  • Calculation and Example of ASR-9 Average fp
  • Synchronizers in Redundant Radar Channels
  • Interference between Channels
  • Review Questions
  • Answers to Review Questions

Inspec keywords: airborne radar; magnetrons; built-in self test; synchronisation

Other keywords: BIT functions; range-elevation-azimuth three-dimensional systems; transmitter triggers; STC triggers; time 741 mus; coho gate; magnetron systems; live-time gates; ASR-9 MTD system; radar synchronizer design; display triggers; ASR radar system; timing triggers; time 2471 mus; MTI system; timing signals; built-in-test functions; distance 60 mile

Subjects: Production facilities and engineering; Radar equipment, systems and applications; Microwave tubes

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