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How Chips Are Made

How Chips Are Made

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Chapter Contents:

  • 12 How Chips Are Made
  • 12.1 IC Fabrication Overview
  • 12.2 Wafer Construction
  • 12.3 Front and Back End of Line Fabrication
  • 12.4 FOL Fab Techniques
  • 12.4.1 Oxidation of Silicon
  • 12.4.2 Photolithography
  • 12.4.3 Etching
  • 12.4.4 Deposition and Implantation
  • 12.5 Cleaning and Safety Operations
  • 12.6 Transistor Fabrication
  • 12.7 Back End of Line BOL Fab Techniques
  • 12.7.1 Sputtering
  • 12.7.2 Dual Damascene
  • 12.7.3 Interlevel Dielectric and Final Passivation
  • 12.8 Fabricating a CMOS Inverter
  • 12.8.1 Front End of Line Operation
  • 12.8.2 Back End of Line Operation
  • 12.9 Die Packaging
  • 12.10 IC Testing
  • 12.11 Summary
  • Reference

Inspec keywords: CMOS integrated circuits; integrated circuit packaging; dielectric materials; semiconductor doping; sawing; integrated circuit design; integrated circuit reliability; photolithography; integrated circuit testing; quality control; silicon compounds; integrated circuit manufacture; vias

Other keywords: SiO2; dielectrics; manufacturing cost; circuit die; Si3N4; vias; diffusion regions; mechanical protection; repetitive photolithography; line voltages; wafer test; node voltages; silicon wafer; diamond saw operation; circuit wells; n-doping; reliability failures; thin oxide; single crystal material; IC packages; p-doping; insulation; doping atoms; fab process; airborne corrosive molecules; size 200 mm; metal layers; polysilicon gates; size 300 mm

Subjects: Product packaging; Lithography (semiconductor technology); Dielectric materials and properties; Metallisation and interconnection technology; CMOS integrated circuits; Semiconductor integrated circuit design, layout, modelling and testing; Semiconductor doping

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