Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

## Hardware precoding demonstration in multibeam UHTS communications under realistic payload characteristics

• Author(s):
• DOI:

$16.00 (plus tax if applicable) ##### Buy Knowledge Pack 10 chapters for$120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:

Advances in Communications Satellite Systems: Proceedings of the 37th International Communications Satellite Systems Conference (ICSSC-2019) — Recommend this title to your library

## Thank you

In this chapter, we present a new hardware test-bed to demonstrate closed-loop precoded communications for interference mitigation in multibeam ultrahigh throughput satellite systems under realistic payload and channel impairments. We build the test-bed to demonstrate a real-time channel aided precoded transmission under realistic conditions such as the power constraints and satellite-payload nonlinearities. We develop a scalable architecture of an SDR platform with the DVB-S2X piloting. The SDR platform consists of two parts: analog-to-digital (ADC) and digital-to-analog (DAC) converters preceded by radio frequency (RF) front end and field-programmable gate array (FPGA) backend. The former introduces realistic impairments in the transmission chain such as carrier frequency and phase misalignments, quantization noise of multichannel ADC and DAC, and nonlinearities of RF components. It allows evaluating the performance of the precoded transmission in a more realistic environment rather than using only numerical simulations. We benchmark the performance of the communication standard in realistic channel scenarios, evaluate received signal SNR, and measure the actual channel throughput using LDPC codes.

Chapter Contents:

• 66.1 Introduction
• 66.2 Hardware demonstrator
• 66.2.1 System model
• 66.2.2 Gateway
• 66.2.3 Channel emulator
• 66.2.4 User terminal
• 66.2.4.1 LLR demapper
• 66.2.4.2 LDPC decoder
• 66.2.5 Resource occupation in FPGAs
• 66.3 Conclusion
• Acknowledgments
• References

Preview this chapter:

Hardware precoding demonstration in multibeam UHTS communications under realistic payload characteristics, Page 1 of 2

| /docserver/preview/fulltext/books/te/pbte095e/PBTE095E_ch66-1.gif /docserver/preview/fulltext/books/te/pbte095e/PBTE095E_ch66-2.gif

### Related content

content/books/10.1049/pbte095e_ch66
pub_keyword,iet_inspecKeyword,pub_concept
6
6
This is a required field