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Cryptographic engines for cloud based on FPGA

Cryptographic engines for cloud based on FPGA

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Cryptographic operations are being performed in all security critical applications and devices. Encryption/Decryption and authentication operations are used in the cloud server for full virtual machine encryption, protection of data at rest, data in motion, etc. Execution of cryptographic operations on the processor reduces the efficiency and increases heat production. Integration of fieldprogrammable gate array (FPGA) devices to cloud data centers opens up the opportunity to implement critical tasks in hardware, thereby improving the efficiency. Security being a critical application on cloud can be implemented on hardware to improve performance and reduce heat production. This chapter presents hardware implementation of four cryptographic engines-AES, DES, SHA, and MD5 on FPGA. Finally, an adaptive reconfigurable security system with the four cryptographic engines using partial reconfiguration is discussed. Depending on the dynamic need, only the necessary algorithm can be loaded which saves power and area.

Chapter Contents:

  • 11.1 Introduction
  • 11.1.1 Field-programmable gate array (FPGA)
  • 11.1.2 Cryptographic algorithms for encryption and authentication
  • 11.1.3 Need of hardware cryptographic engines for cloud servers
  • 11.2 Advanced encryption standard
  • 11.2.1 Hardware realization of AES on FPGA
  • 11.2.1.1 Substitute Byte
  • 11.2.1.2 Merging of Substitute Byte and Shift Rows
  • 11.2.1.3 Mix Column
  • 11.2.1.4 Key Expansion
  • 11.2.1.5 Add Round Key
  • 11.2.2 Efficiency of the system
  • 11.3 Data encryption standard (DES) hardware accelerator
  • 11.3.1 DES
  • 11.3.2 Hardware realization of DES
  • 11.3.2.1 Initial permutation
  • 11.3.2.2 Feistel round
  • 11.3.2.3 Expansion P-box
  • 11.3.2.4 XOR key
  • 11.3.2.5 Substitution boxes
  • 11.3.2.6 Permutation box P
  • 11.3.2.7 32-bit Swap
  • 11.3.2.8 Inverse initial permutation
  • 11.3.2.9 Efficiency of the system
  • 11.4 Secure hash algorithm (SHA-256)
  • 11.4.1 Block decomposition
  • 11.4.2 Round function
  • 11.4.3 Efficiency of the system
  • 11.5 MD5
  • 11.5.1 Processing of message block
  • 11.5.2 Compression function
  • 11.5.3 Efficiency of the system
  • 11.6 Dynamic partial reconfiguration (DPR)
  • 11.7 Security system with AES, DES, SHA, and MD5 using DPR
  • 11.7.1 Partial reconfiguration controller (PRC)
  • 11.8 Future direction
  • References

Inspec keywords: field programmable gate arrays; virtual machines; cloud computing; computer centres; cryptography

Other keywords: cryptographic engines; security critical applications; virtual machine encryption; heat production; decryption; field programmable gate array devices; authentication operations; FPGA; cloud data centers; adaptive reconfigurable security system; cryptographic operations; hardware implementation; cloud server

Subjects: Data security; Internet software; Logic circuits; Logic and switching circuits; Computer facilities; Cryptography; Computer engineering

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