Layout design and parasitic management

Layout design and parasitic management

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The high-speed switching performance of WBG devices poses unique challenges for circuit layout design and parasitics management. This chapter aims at understanding the impact ofparasitics on the switching behavior, investigating the layout design principle for a DPT board, and presenting several case study examples to illustrate the way to apply this design theory in actual implementations.

Chapter Contents:

  • 6.1 Impact of parasitics on the switching performance
  • 6.1.1 Gate loop parasitics
  • 6.1.2 Power loop parasitics
  • 6.1.3 Common parasitics
  • 6.2 DPT layout design
  • 6.3 Case study
  • 6.3.1 Brief overview of WBG devices' package
  • 6.3.2 Case study 1: TO-247 package SiC MOSFETs
  • Placement design for effective lead length minimization
  • PCB layout design for trace parasitics minimization
  • 6.3.3 Case study 2: surface-mount WBG device
  • 6.3.4 With consideration of current measurement in DPT
  • 6.3.5 Gate drive
  • 6.4 Summary
  • References

Inspec keywords: integrated circuit layout

Other keywords: switching behavior; parasitic management; circuit layout design; high-speed switching performance; design theory; WBG devices; parasitics management; layout design principle; DPT board

Subjects: Semiconductor integrated circuit design, layout, modelling and testing

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