The current trends in building clusters and supercomputers are to use medium-to-big symmetric multi-processors (SMP) nodes connected through a high-speed network. Applications need to accommodate to these execution environments using distributed and shared memory programming, and thus become hybrid. Hybrid applications are written with two or more programming models, usually message passing interface (MPI) [1,2] for the distributed environment and OpenMP [3,4] for the shared memory support. The goal of this chapter is to show how the two programming models can be made interoperable and ease the work of the programmer. Thus, instead of asking the programmers to code optimizations targeting performance, it is possible to rely on the good interoperability between the programming models to achieve high performance. For example, instead of using non-blocking message passing and double buffering to achieve computation-communication overlap, our approach provides this feature by taskifying communications using OpenMP tasks [5,6].

Chapter Contents:

• 1.1 MPI+OmpSs interoperability
• 1.2 The interposition library
• 1.3 Implementation of the MPI+OmpSs interoperability
• 1.4 Solving priority inversion
• 1.5 Putting it all together
• 1.6 Machine characteristics
• 1.7 Evaluation of NTChem
• 1.7.1 Application analysis
• 1.7.2 Parallelization approach
• 1.7.3 Performance analysis
• 1.8 Evaluation with Linpack
• 1.8.1 Application analysis
• 1.8.2 Parallelization approach
• 1.8.3 Performance analysis
• 1.9 Conclusions and future directions
• Acknowledgments
• References

Inspec keywords: parallel processing; shared memory systems; multiprocessing systems; mainframes; open systems; message passing

Other keywords: HPC; SMP; programming models; OpenMP; medium-to-big symmetric multi-processors; MPI; shared memory support; many core processors; message passing interface

Subjects: Parallel software; Multiprocessing systems; Distributed systems software; Computer networks and techniques; Parallel programming and algorithm theory; Parallel architecture