Increasing demands to process large amounts of data in real time leads to an increase in the many-core microprocessors, which is posing a grand challenge for an effective and management of available resources. As communication power occupies a significant portion of power consumption when processing such big data, there is an emerging need to devise a methodology to reduce the communication power without sacrificing the performance. To address this issue, we introduce a cognitive I/O designed toward 3D-integrated many-core microprocessors that performs adaptive tuning of the voltage-swing levels depending on the achieved performance and power consumption. We embed this cognitive I/O in a many-core microprocessor with DRAM memory partitioning to perform energy saving for application such as fingerprint matching and face recognition.

Chapter Contents:

• 19.1 Introduction
• 19.2 Cognitive I/O architecture for 3D memory-logic integration
• 19.2.1 System architecture
• 19.2.2 QoS-based I/O management problem formulation
• 19.3 I/O QoS model
• 19.3.1 Sparse representation theory
• 19.3.2 Input data dimension reduction by projection
• 19.3.3 I/O QoS optimization
• 19.3.4 I/O QoS cost function
• 19.4 Communication-QoS-based management
• 19.4.1 Cognitive I/O design
• 19.4.2 Simulation results
• 19.4.2.1 Experiment setup
• 19.4.2.2 Adaptive tuning by cognitive I/O
• 19.4.2.3 Adaptive I/O control by accelerated Q-learning
• 19.5 Performance-QoS-based management
• 19.5.1 Dimension reduction
• 19.5.2 DRAM partition
• 19.5.3 Error tolerance
• 19.5.4 Feature preservation
• 19.5.5 Simulation results
• 19.6 Hybrid QoS-based management
• 19.6.1 Hybrid management via memory (DRAM) controller
• 19.6.2 Communication-QoS result
• 19.6.3 Performance-QoS result
• 19.7 Conclusion and future directions
• References

Inspec keywords: face recognition; microprocessor chips; DRAM chips; fingerprint identification; power consumption

Other keywords: big data; grand challenge; cognitive; many-core microprocessor; communication power; 3D-integrated many-core microprocessors; achieved performance; effective management; power consumption; voltage-swing levels; 3D-integrated many-core system

Subjects: Microprocessors and microcomputers; Semiconductor storage; Microprocessor chips; Computer vision and image processing techniques; Memory circuits; Image recognition