Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

Modelling many-core architectures

Modelling many-core architectures

For access to this article, please select a purchase option:

Buy chapter PDF
$16.00
(plus tax if applicable)
Buy Knowledge Pack
10 chapters for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Many-Core Computing: Hardware and Software — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

Architectural modelling has two primary objectives: (1) navigating the design space exploration, i.e. guiding the architects to arrival at better design choices, and (2) facilitating dynamic management, i.e. providing the functional relationships between workloads'characteristics and architectural configurations to enable appropriate runtime hardware/software adaptations. In the past years, many-core architectures, as a typical computing fabric evolving from the monolithic single-/multicore architectures, have been shown to be scalable to uphold the staggering the Moore's Law. The many-core architectures enable two orthogonal approaches, scale-up and scale-out, to utilize the growing budget of transistors. Understanding the rationale behind these approaches is critical to make more efficient use of the powerful computing fabric.

Chapter Contents:

  • 12.1 Introduction
  • 12.2 Scale-out vs. scale-up
  • 12.3 Modelling scale-out many-core
  • 12.3.1 CPR model
  • 12.3.2 α Model
  • 12.4 Modelling scale-up many-core
  • 12.4.1 PIE model
  • 12.4.2 β Model
  • 12.5 The interactions between scale-out and scale-up
  • 12.5.1 φ Model
  • 12.5.2 Investigating the orthogonality assumption
  • 12.6 Power efficiency model
  • 12.6.1 Power model
  • 12.6.2 Model calculation
  • 12.7 Runtime management
  • 12.7.1 MAX-P: performance-oriented scheduling
  • 12.7.2 MAX-E: power efficiency-oriented scheduling
  • 12.7.3 The overview of runtime management
  • 12.8 Conclusion and future directions
  • Acknowledgements
  • References

Inspec keywords: power aware computing; microprocessor chips; hardware-software codesign; embedded systems; multiprocessing systems; parallel architectures

Other keywords: architectural configurations; design space exploration; architectural modelling; appropriate runtime hardware-software adaptations; primary objectives; single-multicore architectures; many-core architectures; design choices

Subjects: Multiprocessing systems; Digital circuit design, modelling and testing; Hardware-software codesign; Microprocessor chips; Microprocessors and microcomputers; Parallel architecture

Preview this chapter:
Zoom in
Zoomout

Modelling many-core architectures, Page 1 of 2

| /docserver/preview/fulltext/books/pc/pbpc022e/PBPC022E_ch12-1.gif /docserver/preview/fulltext/books/pc/pbpc022e/PBPC022E_ch12-2.gif

Related content

content/books/10.1049/pbpc022e_ch12
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address