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Modelling many-core architectures

Modelling many-core architectures

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Architectural modelling has two primary objectives: (1) navigating the design space exploration, i.e. guiding the architects to arrival at better design choices, and (2) facilitating dynamic management, i.e. providing the functional relationships between workloads'characteristics and architectural configurations to enable appropriate runtime hardware/software adaptations. In the past years, many-core architectures, as a typical computing fabric evolving from the monolithic single-/multicore architectures, have been shown to be scalable to uphold the staggering the Moore's Law. The many-core architectures enable two orthogonal approaches, scale-up and scale-out, to utilize the growing budget of transistors. Understanding the rationale behind these approaches is critical to make more efficient use of the powerful computing fabric.

Chapter Contents:

  • 12.1 Introduction
  • 12.2 Scale-out vs. scale-up
  • 12.3 Modelling scale-out many-core
  • 12.3.1 CPR model
  • 12.3.2 α Model
  • 12.4 Modelling scale-up many-core
  • 12.4.1 PIE model
  • 12.4.2 β Model
  • 12.5 The interactions between scale-out and scale-up
  • 12.5.1 φ Model
  • 12.5.2 Investigating the orthogonality assumption
  • 12.6 Power efficiency model
  • 12.6.1 Power model
  • 12.6.2 Model calculation
  • 12.7 Runtime management
  • 12.7.1 MAX-P: performance-oriented scheduling
  • 12.7.2 MAX-E: power efficiency-oriented scheduling
  • 12.7.3 The overview of runtime management
  • 12.8 Conclusion and future directions
  • Acknowledgements
  • References

Inspec keywords: power aware computing; microprocessor chips; hardware-software codesign; embedded systems; multiprocessing systems; parallel architectures

Other keywords: architectural configurations; design space exploration; architectural modelling; appropriate runtime hardware-software adaptations; primary objectives; single-multicore architectures; many-core architectures; design choices

Subjects: Multiprocessing systems; Digital circuit design, modelling and testing; Hardware-software codesign; Microprocessor chips; Microprocessors and microcomputers; Parallel architecture

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