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Modelling interconnects for future VLSI circuit applications

Modelling interconnects for future VLSI circuit applications

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VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects — Recommend this title to your library

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This chapter discusses the various methods of electrical modelling of CNT- and GNR-based nano-interconnects. It also presents the ABCD parameter matrix-based method for the modelling of performance and signal integrity effects in CNT- and GNR-based VLSI nano-interconnects. The developed methodology is proven to be almost 100% accurate as SPICE with huge reduction in the computational burden. It is pointed out that both CNTs and GNRs have tremendous potential in becoming the next generation VLSI interconnects.

Chapter Contents:

  • 7.1 Issues with nano-electronic interconnects
  • 7.2 Electrical equivalent circuit modelling of CNT-and GNR-based interconnects
  • 7.2.1 Equivalent circuit parameters of SWCNT
  • 7.2.2 Equivalent RLC parameters of SWCNT bundle
  • 7.2.3 Equivalent RLC parameters of MWCNT bundle interconnect
  • 7.2.3.1 Equivalent RLC parameters of an isolated large diameter MWCNT bundle interconnect
  • 7.2.3.2 Equivalent RLC parameters of an isolated small diameter MWCNT bundle interconnect
  • 7.2.4 Equivalent RLC parameters of DWCNT bundle
  • 7.2.5 Electrical modelling of multilayer graphene nanoribbon interconnects
  • 7.3 Delay estimation of CNT-and GNR-based nano-interconnects
  • 7.3.1 ABCD parameter-based delay model
  • 7.4 Crosstalk modelling of CNT and GNR interconnects
  • 7.4.1 Crosstalk and transient analysis in interconnects
  • 7.4.2 ABCD parameter-based approach
  • 7.4.3 Simulation methodology
  • 7.5 Modelling of reliability issues in CNT and GNR interconnects
  • 7.6 Summary and future work
  • References

Inspec keywords: VLSI; integrated circuit interconnections; graphene; nanoribbons; SPICE; nanoelectronics; carbon nanotubes

Other keywords: carbon nanotubes; electrical modelling; GNR-based VLSI nanointerconnects; VLSI circuit applications; C; CNT-based VLSI nanointerconnects; ABCD parameter matrix-based method; signal integrity effects; next generation VLSI interconnects; graphene nanoribbons; performance modelling

Subjects: Fullerene, nanotube and related devices; Semiconductor integrated circuit design, layout, modelling and testing; Metallisation and interconnection technology

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