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Design and analysis of variability aware FinFET-based SRAM circuit design

Design and analysis of variability aware FinFET-based SRAM circuit design

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In modern SOC design SRAM has become an integral part owing to its capability to form a bridge and overcome the speed mismatch problem between the high speed processor and the low speed data storage devices. Because of the read and write operation of SRAM cell having conflicting transistor sizing requirement, it is very difficult to maintain the transistor size to satisfy both the needs. The destructive nature of read operation enforces a serious thought about SRAM cell data stability. Transistor sizing and cell stability already being a critical problem becomes even more critical when we consider the process and temperature variation. Thus the SRAM should be designed with keeping the process and temperature variation in mind. The random fluctuation in device parameters such as transistor width, length, oxide thickness, oxide capacitance and doping concentration leads to variation in the threshold voltage and other transistor characteristics. The change in these transistor characteristics alters the SRAM cell performance. Hence this should also be taken care of to ensure the cell performance to be in the desired range even in presence of random fluctuation during fabrication process. The various performance measure such as SNM, write SNM, speed and power consumption must be tested under worst process corner as well over a wide temperature range to ensure that they lie in the acceptable range during worst operating condition. Also these parameters must be tested using Monte Carlo simulation to ensure a robust operation in presence of random fluctuation during fabrication process.

Chapter Contents:

  • 6.1 Introduction
  • 6.2 SRAM in memory hierarchy
  • 6.3 Basic SRAM performance indices
  • 6.3.1 Energy consumption
  • 6.3.2 Stability
  • 6.3.3 Speed
  • 6.3.4 Area occupancy
  • 6.4 FinFET as a substitute to MOSFET
  • 6.5 Techniques to make SRAM process variation aware
  • 6.5.1 SRAM design with awareness of static noise margin variation
  • 6.5.2 SRAM design with awareness of process corner variation
  • 6.5.3 SRAM design with awareness of temperature variation
  • 6.5.4 SRAM design with awareness of supply voltage variation
  • 6.5.5 SRAM design with awareness of random fluctuation in device parameters
  • 6.5.6 SRAM design with awareness of fluctuation in write ability
  • 6.6 Summary
  • References

Inspec keywords: MOSFET circuits; SRAM chips; Monte Carlo methods; integrated circuit design; circuit stability

Other keywords: temperature variation; SOC design; speed mismatch problem; read operation; low speed data storage devices; high speed processor; random fluctuation; variability aware FinFET-based SRAM circuit design; transistor characteristics; threshold voltage; process variation; SRAM cell data stability; fabrication process; Monte Carlo simulation; transistor sizing requirement

Subjects: Monte Carlo methods; Monte Carlo methods; Memory circuits; Semiconductor storage

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