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Impact of oxide thickness variation on the performance of junctionless FinFET

Impact of oxide thickness variation on the performance of junctionless FinFET

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VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects — Recommend this title to your library

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The relentless advances in the complementary metal oxide semiconductor (CMOS) technology have mainly enabled through dimensional downscaling of the transistor which brings out numerous challenges such as controlling short channel effects (SCEs), leakage current and fabrication complexity of forming high-quality metallurgical junction at sub-nanoscale regime. Junctionless (JL) concept in the transistor has emerged recently and shown tremendous potential for the future technology generation. It not only simplified the fabrication process but also provided the comparable performance to those of conventional junction-based metal oxide semiconductor (MOS) devices. This work, for the first time, demonstrates the impact of oxide thickness variation (OTV) on a 14 nm junctionless FinFET (JL FinFET) using extensive technology computer-aided design (TCAD) device simulation. Results show that the deviation in threshold voltage and OFF-current are seriously impacted by OTV for JL FinFET structure as compared to the normal inversion mode (IM) counterparts. Furthermore, the joint impact of all the intrinsic statistical variability sources including OTV, random dopant fluctuation (RDF) and gate work function variation (WFV) on threshold voltage has been investigated.

Chapter Contents:

  • 5.1 Introduction
  • 5.2 OTV: a theoretical outlook
  • 5.3 Device design and simulation approach
  • 5.4 OTV modelling
  • 5.5 Results and discussion
  • 5.5.1 OTV-induced variability
  • 5.5.2 Joint impact of RDF, OTV and WFV
  • 5.6 Summary
  • References

Inspec keywords: semiconductor device models; technology CAD (electronics); leakage currents; MOSFET; work function

Other keywords: future technology generation; complementary metal oxide semiconductor technology; oxide thickness variation; leakage current; size 14.0 nm; dimensional downscaling; sub-nanoscale regime; junction-based metal oxide semiconductor devices; OTV; short channel effects; gate work function variation; junctionless FinFET; high-quality metallurgical junction; JL FinFET structure; fabrication process; intrinsic statistical variability sources; extensive technology computer-aided design device simulation; current fabrication complexity; junctionless concept; random dopant fluctuation; threshold voltage

Subjects: Insulated gate field effect transistors; Semiconductor device modelling, equivalent circuits, design and testing

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