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UTB III–V-OI-Si MOS transistor: the future transistor for VLSI design

UTB III–V-OI-Si MOS transistor: the future transistor for VLSI design

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In power-constrained very large scale integration (VLSI) design, the transistors need to operate with extremely scaled supply voltage ( 0.4-0.5 V) and must have good electrostatic integrity to minimize the static power dissipation. But these lead to compromise in switching speed. This competing requirement necessitates the introduction of new material to form the channel of a MOS transistor, in which the inversion charge carriers travel with much higher velocity than that in silicon. With this, the loss of switching speed can be reduced. III-V compound semiconductors such as GaAs, InGaAs and InAs have very good electron transport properties. The mobility of electrons in InGaAs or InAs is more than ten times higher than that for silicon at a comparable sheet charge density [1]. However, one intrinsic drawback of the MOS transistor made of III-V semiconductors is worse device electrostatic integrity. Therefore, ultrathin body (UTB) structures like UTB-on-insulator (UTBOI) structure, FinFET or trigate structure and nanowire field effect transistor (FET) structure with III-V-based channel material have gained attention of the semiconductor device researchers for applications in next generation VLSI circuits. It may be noted that any new technology is desired to be compatible with an Si-based CMOS platform for cost-effective mass production and system-on-chip applications. Direct wafer bonding (DWB) technique is an important approach to grow III-V-OI structures with thin buried oxide (BOX) layers on Si wafers. This chapter provides a comprehensive overview of a UTB III-V-OI-Si MOS transistor. The advantages of using III-V channel materials over Si are summarized using calibrated technology computer-aided design (TCAD) simulation results. Gate-source/drain (G-S/D) underlap technique is discussed as an approach to enhance electrostatic integrity. Finally, UTB, GaAs-OI structure is briefly introduced as a candidate for a p-channel MOS transistor.

Chapter Contents:

  • 2.1 Carrier transport properties of III–V semiconductors
  • 2.2 Device description and fabrication process of a III–V-OI-Si MOS transistor
  • 2.3 Technology computer-aided design (TCAD) and simulation framework
  • 2.4 Comparison between III–V-OI-Si and SOI MOS transistors
  • 2.5 Electrostatic integrity and gate-induced drain leakage in III–V-OI-Si transistors
  • 2.5.1 Gate–source/drain underlap technique
  • 2.5.2 Effects of scaling of buried oxide layer
  • 2.6 GaAs-OI junction-less PMOS transistor
  • 2.7 Summary
  • Acknowledgment
  • References

Inspec keywords: III-V semiconductors; VLSI; technology CAD (electronics); MOSFET

Other keywords: Si-based CMOS platform; ultrathin body structures; III-V-based channel material; switching speed; GaAs-OI structure; power-constrained very large scale integration design; VLSI design; p-channel MOS transistor; III-V compound semiconductors; III-V-OI structures; UTB-on-insulator structure; UTB III-V-OI-Si MOS transistor; static power dissipation

Subjects: Semiconductor device modelling, equivalent circuits, design and testing; Insulated gate field effect transistors

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