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Transient fault secured/tolerant architecture for DSP core

Transient fault secured/tolerant architecture for DSP core

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In this chapter we have provided a detailed description to TFs, its origin and its impact on integrated circuits. Further, we have discussed recent state-of-the-art methodologies present in the literature that provides security and/or tolerance subsequent CS doesn't require shifting of primary outputs. Hence, overall schedule delay is not affected. Similarly, as shown in Figure 16.15, for k = 10 and k m = 4, a small increment in the delay for [4] in case of large size benchmarks is observed. However, the delay overhead is within acceptable limits. (Note: during above delay comparison the delay overhead of two CS due to comparators and voter is not considered for analysis of delay overhead. This was done to provide analysis of delay overhead resulting only due to shifting of operations during scheduling and allocation.)

Chapter Contents:

  • 16.1 Introduction
  • 16.2 Background of transient faults
  • 16.2.1 Motivation
  • 16.2.2 Reasons for transient faults
  • 16.2.3 Transient fault security versus tolerance
  • 16.3 Models for DSP core
  • 16.3.1 Design objectives of DSP core
  • 16.3.2 Evaluation function for DSP core
  • 16.4 Selected TF secured/tolerant approaches for DSP core
  • 16.4.1 Multicycle tolerant approach for DSP cores
  • 16.4.1.1 Description of the algorithm
  • 16.4.1.2 Demonstrative example on finite impulse response (FIR) filter
  • 16.4.2 Fault secured approach for DSP cores
  • 16.4.2.1 Description of the algorithm
  • 16.4.2.2 Demonstrative example on FIR filter
  • 16.4.3 Fault tolerant approach for DSP cores
  • 16.4.3.1 Description of the algorithm
  • 16.4.3.2 Demonstrative example on FIR filter
  • 16.5 Analysis and comparison
  • 16.5.1 Transient fault security
  • 16.5.1.1 Delay comparison of [4] w.r.t. nonsecured DMR
  • 16.5.1.2 Area comparison of [4] w.r.t. nonsecured DMR
  • 16.5.2 Transient fault tolerance
  • 16.6 Summary
  • Acknowledgements
  • References

Inspec keywords: fault tolerance; fault diagnosis; digital signal processing chips

Other keywords: transient fault secured-tolerant architecture; integrated circuits; DSP core; security

Subjects: Digital signal processing chips; Digital signal processing chips

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