http://iet.metastore.ingenta.com
1887

Methods to design ternary gates and adders

Methods to design ternary gates and adders

For access to this article, please select a purchase option:

Buy chapter PDF
$16.00
(plus tax if applicable)
Buy Knowledge Pack
10 chapters for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

This chapter contains various designs of ternary logic gates and adders using complementary metal oxide semiconductor transistors (CMOS) and carbon nanotube field effect transistors (CNTFETs). As the time goes by binary logic is getting harder to implement on smaller scale, so ternary logic becomes a better alternative of the same. Ternary logic has the simplicity over binary logic and it is energy efficient also. In today's world when it's a challenge to implement the circuit design on as small level as possible, binary logic is limited due to large number of interconnects and large chip area, which is reduced in ternary logic. In ternary logic, there is a requirement of the multithreshold transistors, which can switch on and switch off on the particular voltage level when the circuit demands, since CNTFET's threshold can be changed by varying their chirality or tube diameter they have become the most suitable devices to implement ternary logic. In this chapter various research works on ternary gates and adders will be discussed and a comparison between them will be made on various performance parameters such as power delay product (PDP), transistor count and time delay. These parameters are evaluated and compared by simulating these circuits.

Chapter Contents:

  • 14.1 Introduction
  • 14.2 Carbon nanotube field effect transistor
  • 14.3 Ternary inverters
  • 14.4 Ternary gates
  • 14.5 Ternary adders
  • 14.5.1 Decoder circuit
  • 14.5.2 Sum circuit
  • 14.5.2.1 Adder 1
  • 14.5.2.2 Adder 2
  • 14.5.2.3 Adder 3
  • 14.5.3 Buffers
  • 14.5.3.1 Transient response
  • 14.5.4 Comparative evaluation
  • References

Inspec keywords: carbon nanotube field effect transistors; adders; CMOS logic circuits; logic design; logic gates; ternary logic

Other keywords: CMOS; carbon nanotube field effect transistors; power delay product; multithreshold transistors; circuit design; adders; complementary metal oxide semiconductor transistors; binary logic; ternary logic gates; CNTFET; transistor count

Subjects: Logic circuits; CMOS integrated circuits; Logic design methods; Other field effect devices; Digital circuit design, modelling and testing; Logic elements; Logic and switching circuits; Fullerene, nanotube and related devices

Preview this chapter:
Zoom in
Zoomout

Methods to design ternary gates and adders, Page 1 of 2

| /docserver/preview/fulltext/books/cs/pbcs073g/PBCS073G_ch14-1.gif /docserver/preview/fulltext/books/cs/pbcs073g/PBCS073G_ch14-2.gif

Related content

content/books/10.1049/pbcs073g_ch14
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address