Composite PFD based low-power, low noise, fast lock-in PLL

Composite PFD based low-power, low noise, fast lock-in PLL

For access to this article, please select a purchase option:

Buy chapter PDF
(plus tax if applicable)
Buy Knowledge Pack
10 chapters for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
VLSI and Post-CMOS Electronics. Volume 1: Design, modelling and simulation — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

It has been found that the proposed PLL design results in reduced lock time and reference spur while maintaining stable closed -loop operation. Composite PFD provides high gain and high loop band width (BW) during lock -in and lower loop BW after getting locked -in resulting in improvement in lock -in and noise characteristics. NL-PFD helps in eliminating blind zone, and linear PFD helps in eliminating dead zone while suppressing unwanted glitches completely from the output of the PFDs resulting in reduced reference spur. Charge pump and LF topology have been developed so as to maintain constant phase margin to ensure stability during tracking and after lock -in. A prototype of PLL operating at 2.56 GHz developed with 180 nm CMOS process is found to achieve reference spur of -71.4 dB c at 20 MHz offset.

Chapter Contents:

  • 6.1 Proposed composite PFD architecture
  • 6.1.1 Transistor level implementation of NL-PFD3
  • 6.1.2 Transistor level implementation of L-PFD3
  • 6.2 Proposed PLL architecture
  • 6.2.1 Charge pump and VCO in the PLL
  • 6.3 Design of novel PLL architecture using composite PFD and variable loop filter
  • 6.4 State-space analysis of PLL architecture
  • 6.5 Post layout simulation analysis of novel PLL architecture
  • 6.5.1 Trade-off between power and frequency
  • 6.5.2 Lock-time analysis
  • 6.5.3 Phase-noise analysis of novel PLL architecture
  • 6.5.4 Reference spur
  • 6.5.5 Jitter
  • 6.5.6 PVT analysis of proposed PLL
  • 6.5.7 Discussion
  • 6.6 Summary
  • References

Inspec keywords: integrated circuit design; CMOS integrated circuits; UHF integrated circuits; low-power electronics; phase locked loops; charge pump circuits; phase detectors

Other keywords: composite PFD; gain -71.4 dB; stability; size 180 nm; dead zone elimination; CMOS process; low-power low noise fast lock-in PLL design; NL-PFD; charge pump; frequency 2.56 GHz; LF topology; phase frequency detectors

Subjects: CMOS integrated circuits; Microwave integrated circuits; Other analogue circuits; Semiconductor integrated circuit design, layout, modelling and testing; Power electronics, supply and supervisory circuits; Modulators, demodulators, discriminators and mixers

Preview this chapter:
Zoom in

Composite PFD based low-power, low noise, fast lock-in PLL, Page 1 of 2

| /docserver/preview/fulltext/books/cs/pbcs073f/PBCS073F_ch6-1.gif /docserver/preview/fulltext/books/cs/pbcs073f/PBCS073F_ch6-2.gif

Related content

This is a required field
Please enter a valid email address