This chapter explores the design space of proposed M7T, MPT8T, M8T, M9T and MI-12T SRAM cells implemented at 45 nm technology node which are suitable for subthreshold operation. For quick comparison, Figure 3.45 shows the comparative design space exploration (DSE) chart of SRAM cells at 45 nm technology, respectively. The thorough analyses on the impacts of read stability, write ability, average write delay, average read delay and leakage power consumption in hold mode have been summarized in Table 3.14. The proposed memory cells exhibit improvement in performance over C6T.

Chapter Contents:

• 3.1 Introduction
• 3.2 Design and operation of C6T
• 3.3 Design and operation of proposed SRAM cells at 45 nm
• 3.3.1 Design of proposed MPT8T using PN access transistor
• 3.3.2 Design of proposed M8T using NN-parallel access transistor
• 3.3.3 Design of proposed MI-12T
• 3.3.4 Design of proposed M7T
• 3.3.5 Design of proposed M9T
• 3.4 Results and analysis
• 3.4.1 SRAM standby stability analysis (hold stability)
• 3.4.2 SRAM read stability analysis
• 3.4.3 SRAM write ability analysis
• 3.4.4 Alternative noise margins
• 3.4.5 Read access time (TRA) with variability
• 3.4.6 Write access time (TWA) with variability
• 3.4.7 Leakage power consumption in hold mode
• 3.5 Analytical expressions for hold SNM, RSNM and WSNM of SRAM cells
• 3.6 Performance analysis and discussion
• 3.7 Summary
• References

Inspec keywords: SRAM chips; low-power electronics; circuit stability; integrated circuit design

Other keywords: DSE chart; M9T SRAM cells; size 45 nm; read stability; hold mode; low-voltage low-power SRAM circuits; subthreshold design technique; M8T SRAM cells; MI-12T SRAM cells; MPT8T SRAM cells; leakage power consumption; design space exploration; M7T SRAM cells; subthreshold operation; write ability; average read delay; average write delay; memory cells

Subjects: Memory circuits; Semiconductor storage; Semiconductor integrated circuit design, layout, modelling and testing