Intel declared 2016 as the end of Moore's prediction. Researchers and academicians are exploring other alternatives to fulfill the latency between the processor and memory system. A universal memory is required that can be used at the various levels of memory hierarchy. STT-MRAM has shown the promising features to be used at various levels of memory hierarchy. In this chapter, we discussed the GMR, TMR, and STT as the basic phenomena required for STT-MRAM reading and writing. Conversion of charge current to spin-polarized current is explained with the help of Bloch states of different symmetries. I-MTJ and P-MTJ are explained using key performance parameters such as thermal stability and critical current. Working of STT-MRAM bit cell is discussed using NMOS transistor as an access device. Framework for low power hybrid MTJ/CMOS circuits is explained using PCSA, CMOS logic tree, and nonvolatile input store in terms of relative magnetization state of MTJs. STT-MRAM faces the challenges of high write energy, reliability, and read disturbance due to common read and write path. To mitigate these issues, SOT-based device and fast-switching mechanism VCMA has been suggested. Finally, based on the performance of STT-MRAM, it can be projected that low-power operations can be achieved using STT-MRAM as a working memory. Further, high-speed and low-power operations can be attained with hybrid MTJ/CMOS nonvolatile core circuits. The recent developments in the spintronics field have opened the door for energy-saving and high-performance electronics from device level to circuit level.

Chapter Contents:

• 10.1 Introduction
• 10.2 Thrust for emerging nonvolatile memories
• 10.3 Basics of spintronics
• 10.3.1 Giant magnetoresistance
• 10.3.2 Tunneling magnetoresistance
• 10.3.3 Spin-transfer torque
• 10.4 Magnetic tunnel junction
• 10.4.1 In-plane MTJ
• 10.4.2 Perpendicular plane MTJ
• 10.5 Spin-transfer torque magnetic random-access memory
• 10.5.1 Write operation
• 10.5.2 Read operation
• 10.5.3 Performance parameters
• 10.5.4 Challenges for STT-MRAM
• 10.6 Simulation setup
• 10.7 Spintronics-based hybrid MTJ/CMOS circuits
• 10.7.1 Precharged sense amplifier
• 10.7.2 Write circuit
• 10.8 Hybrid MTJ/CMOS logic circuits
• 10.8.1 Hybrid MTJ/CMOS AND/NAND gate
• 10.8.2 Hybrid MTJ/CMOS OR/NOR gate
• 10.8.3 Hybrid MTJ/CMOS XOR/XNOR gate
• 10.9 Magnetic nonvolatile full adder
• 10.10 Device-to-system level
• 10.11 Summary
• References

Inspec keywords: low-power electronics; CMOS logic circuits; trees (electrical); tunnelling magnetoresistance; magnetoelectronics; MRAM devices; magnetic tunnelling; giant magnetoresistance; CMOS memory circuits

Other keywords: spin-polarized current; CMOS logic tree; spintronics memory; NMOS transistor; VCMA fast-switching mechanism; spintronics field; low power hybrid MTJ-CMOS circuits; relative magnetization state; giant magnetoresistance; STT-MRAM reading; low-power operations; Bloch states; in-plane magnetic tunnel junction; TMR; GMR; SOT-based device; Intel; tunneling magnetoresistance; perpendicular plane magnetic tunnel junction; I-MTJ; memory hierarchy; high-performance electronics; critical current; STT-MRAM writing; processor system; energy-saving; nonvolatile input store; thermal stability; P-MTJ; hybrid MTJ-CMOS nonvolatile core circuits; memory system; CMOS technology; high-speed operations; Moore prediction

Subjects: Magneto-acoustic, magnetoresistive, magnetostrictive and magnetostatic wave devices; CMOS integrated circuits; Semiconductor storage; Memory circuits; Electrical/electronic equipment (energy utilisation); Logic and switching circuits; Storage on stationary magnetic media; Logic circuits