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Multi-phase obfuscation for fault-secured DSP circuits

Multi-phase obfuscation for fault-secured DSP circuits

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This chapter discusses a multi-phase obfuscation process for fault-secured intellectual property (IP) cores during electronic system level (ESL) synthesis. A detailed elaboration on the threat model for fault-secured IP cores is followed by the use of the multi-phase obfuscation process for digital signal processing (DSP) circuits and, finally, analyses of case studies. The chapter is organized as follows: Section 7.1 discusses fault-secured IP cores and their needs, followed by different threats to fault-secured IP cores and how to solve them. Section 7.2 focuses on the differences between functional obfuscation and structural obfuscation. Section 7.3 presents the problem formulation for protecting fault-secured IP cores. Section 7.4 discusses selected contemporary structural obfuscation approaches used to date. Section 7.5 provides an overview of the multi-phase obfuscation approach followed by evaluation models used and details of the approach in the context of fault-secured DSP circuits. Section 7.6 demonstrates the multi-phase obfuscation approach on a fault-secured finite impulse response (FIR) filter. Section 7.7 presents analyses based on case studies. Section 7.8 concludes the chapter.

Chapter Contents:

  • 7.1 Introduction
  • 7.2 Functional obfuscation vs. structural obfuscation
  • 7.3 Problem formulation
  • 7.4 Discussion on selected approaches
  • 7.5 Structural obfuscation of fault-secured DSP circuits
  • 7.5.1 Overview
  • 7.5.2 Evaluation models
  • 7.5.2.1 Area model
  • 7.5.2.2 Delay model
  • 7.5.2.3 Cost function
  • 7.5.3 Details of multi-phase obfuscation for fault-secured DSP circuits
  • 7.5.3.1 Phase-1: Structural obfuscation using HLT and FUT
  • 7.5.3.2 Fault-secured design process
  • 7.5.3.3 Phase-2: structural obfuscation using FU reallocation and mux/demux reconfiguration
  • 7.6 Demonstration of structural obfuscation of fault-secured DSP circuits
  • 7.6.1 Demonstration of phase-1 obfuscation
  • 7.6.2 Demonstration of fault-secured design process
  • 7.6.3 Demonstration of phase-2 obfuscation
  • 7.7 Analyses of case studies
  • 7.7.1 Security analysis
  • 7.7.2 Design cost analysis
  • 7.8 Conclusion
  • 7.9 Questions and exercises
  • References

Inspec keywords: security of data; digital signal processing chips; FIR filters

Other keywords: discusses fault-secured IP cores; FIR filter; digital signal processing circuits; fault-secured IP cores; multiphase obfuscation approach; ESL synthesis; contemporary structural obfuscation; fault-secured DSP circuits; fault-secured finite impulse response filter; fault-secured intellectual property; electronic system level; DSP circuits

Subjects: Filtering methods in signal processing; Semiconductor integrated circuits; Digital signal processing; Data security

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