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3D packaging for the integration of heterogeneous systems

3D packaging for the integration of heterogeneous systems

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This paper discusses innovative processing technologies that would allow 3D packaging by the post-fab vertical stacking technique, suitable for the packaging industry. These novel simple processes may pave way towards 3D-stacked ultra-thin devices.

Chapter Contents:

  • 10.1 Three-dimensional integration
  • 10.1.1 3D integration: manufacturing methods
  • 10.2 3D IC technology landscape
  • 10.2.1 Package-level 3D integration
  • 10.2.2 Chip-level 3D integration
  • 10.2.3 Within-die 3D integration
  • 10.2.4 Monolithic 3D integration
  • 10.3 3D heterogeneous integration
  • 10.4 3D stacking of ultra-thin silicon layers with functional MOS devices
  • 10.4.1 Transistor fabrication NMOS and PMOS
  • 10.4.1.1 Ultra-thin silicon transfer using epoxy and Au–In TLP bonding
  • 10.4.2 Vertical stacking process flow
  • 10.4.3 Keep-out zone
  • 10.4.4 Characterization of the transferred devices
  • 10.4.4.1 Diffusion measurements
  • 10.4.4.2 DC electrical measurements
  • 10.4.4.3 Negative differential resistance
  • 10.4.4.4 3-Layer stack with functional devices and DC measurements
  • 10.4.4.5 5-Layer ultra-thin silicon stack
  • 10.4.5 Reliability measurements on the ultra-thin silicon stack
  • 10.4.5.1 Fabrication of two-layer stacks with functional devices
  • 10.4.5.2 Reliability tests
  • 10.4.5.3 DC electrical measurements
  • 10.5 3D integration of heterogeneous dies for fluorescent detection
  • 10.5.1 Individual components fabrication
  • 10.5.1.1 Photodetector fabrication
  • 10.5.1.2 Selection of optical filter
  • 10.5.1.3 Fabrication of the glass fluidic chip with microheater
  • 10.5.2 Hybrid integration
  • 10.5.2.1 Device stacking by epoxy bonding
  • 10.5.2.2 Bonding plastic filters to silicon photodetector
  • 10.5.2.3 Planarization of the bonded filter stack
  • 10.5.2.4 Bonding of the glass fluidic chip
  • 10.5.2.5 Planarization of the fluidic chip and polymer via opening
  • 10.5.2.6 Interconnecting the components in the stack
  • 10.5.3 Device component testing
  • 10.5.3.1 Effect of stacking on photodetector sensitivity
  • 10.5.3.2 Effect of microheater proximity on photodetector sensitivity
  • 10.5.3.3 Platform testing
  • 10.5.4 Experimental results
  • 10.6 Summary
  • References

Inspec keywords: integrated circuit packaging; three-dimensional integrated circuits

Other keywords: heterogeneous systems integration; 3D-stacked ultra-thin devices; packaging industry; processing technologies; 3D packaging; post-fab vertical stacking technique

Subjects: Product packaging; Semiconductor integrated circuits

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