In this chapter, we mostly discussed 2X oversampling digital CDRs, which required multiple high-frequency clock phases for data and edge sampling. In contrast, baud-rate CDRs employ a single clock phase for data and clock recovery, thereby reducing the power consumed in multiphase clock generation and distribution circuits. Interested readers can read more about baud-rate CDRs, their benefits and drawbacks.

Chapter Contents:

• 18.1 Introduction
• 18.2 Design and analysis of digital CDR
• 18.2.1 Bang-bang phase detector (BBPD)
• 18.2.2 Digital loop filter (DLF)
• 18.2.3 Digital-to-analog converter
• 18.2.4 Voltage controlled oscillator
• 18.2.5 Noise analysis of a digital CDR
• 18.2.5.1 Design example
• 18.3 Design techniques for improving standard digital CDR
• 18.3.1 Low-speed digital loop filter
• 18.3.2 Digital frequency control in oscillators
• 18.3.3 Digitally controlled oscillator (DCO)
• 18.3.4 Decoupling JTRAN and JTRACK bandwidth in CDR
• 18.4 Case study I: digital CDR with decoupled JTRAN and JTRACK
• 18.4.1 A 5 Gb/s digital CDR using PRPLL
• 18.4.1.1 Linear analysis of PRPLL-based digital CDR
• 18.5 Case study II: A wide range digital clock and data recovery
• 18.5.1 A 4–10 Gb/s digital clock and data recovery
• 18.5.2 Fractional-N PLL-based DCO
• 18.5.3 Digitally controlled delay line
• 18.5.4 Linear analysis of a wide range CDR
• References

Inspec keywords: clocks; clock and data recovery circuits; digital circuits

Other keywords: edge sampling; single clock phase; data sampling; multiphase clock generation; digital clock and data recovery circuits; 2X oversampling digital CDRs; distribution circuits; multiple high-frequency clock phases; baud-rate CDRs

Subjects: Other digital circuits