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Asynchronous network-on-chips (NoCs) for resource efficient many core architectures

Asynchronous network-on-chips (NoCs) for resource efficient many core architectures

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In this chapter, different GALS approaches for the implementation of embedded NoC architectures were presented. The GALS approach allows for the reduction of the resource requirements at an increased scalability of the NoC without sacrificing performance. The three approaches of synchronous, mesochronous, and asynchronous NoCs were compared. For the mesochronous NoC special synchronizers between the links were implemented. For the asynchronous NoC, the routers were completely realized as an asynchronous circuits. The results have shown that modern design methods (CCOpt design fl ow) allow a good scaling of MPSoCs even for synchronous NoCs. Nevertheless, the asynchronous NoC showed lower area and energy requirement compared to the mesochronous and synchronous implementation, while still providing a comparable performance. When comparing a place and route of an MPSoC, the asynchronous NoC leads to 3.1% less area requirements. The power consumption of an asynchronous router is only 22.4% (0.94 mW in idle state) or 53% (3.94 mW during communication) of the power consumption of a clock -based router. In the last section of the chapter, the global clock tree for an MPSoC with 256 CPUs was examined. The synchronous and mesochronous NoC show almost the same power consumption of about 7.7 mW. Using the asynchronous NoC reduces the power consumption by about 25% (5.78 mW). In addition, the mesochronous and asynchronous variants achieve a 2.6% higher clock frequency.

Chapter Contents:

  • 8.1 Basics of asynchronous NoCs
  • 8.1.1 Mesochronous architectures
  • 8.1.2 Plesiochronous architectures
  • 8.1.3 Heterochronous architectures
  • 8.1.4 Asynchronous architectures
  • 8.2 GALS extensions for embedded multiprocessors
  • 8.2.1 State-of-the art of GALS-based NoC-architectures
  • 8.2.2 The CoreVA-MPSoC
  • 8.2.3 Mesochronous router implementation
  • 8.2.4 Asynchronous router implementation
  • 8.2.5 Design-space exploration of the different GALS-approaches
  • 8.2.5.1 Power consumption
  • 8.2.5.2 Latency and throughput
  • 8.2.5.3 Global clock tree
  • 8.3 Conclusion
  • References

Inspec keywords: integrated circuit design; asynchronous circuits; network-on-chip

Other keywords: power 5.78 mW; asynchronous NoC; clock-based router; embedded NoC architectures; efficiency 2.6 percent; power 0.94 mW; synchronous NoC; GALS approaches; power 3.94 mW; mesochronous NoC; resource efficient many core architectures; CPU; MPSoC; asynchronous network-on-chips; CCOpt design flow

Subjects: Logic and switching circuits; Logic circuits; Network-on-chip; Semiconductor integrated circuit design, layout, modelling and testing; Network-on-chip

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