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Design and test of high-speed asynchronous circuits

Design and test of high-speed asynchronous circuits

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This chapter explores the design and test of high-speed complementary metal oxide semiconductor (CMOS) self -timed circuits. Section 7.1 describes how the properties of CMOS technology itself limit how fast a self -timed circuit can run. Section 7.2 presents our Link and Joint model, a unified point of view of self -timed circuits that allows reasoning about them independently of circuit families and handshake protocols. The model separates communication and storage, done in Links, from computation and fl ow control, done in Joints. The model also separates actions from states. Special go signals enable or disable Joint actions on an individual basis. The individual go signals make it possible to initialize, start, and stop self -timed operations reliably, which is crucial for design as well as for at -speed test, debug, and characterization. Section 7.3 examines design and test aspects of the Weaver, a self -timed nonblocking 8 x 8 crossbar switch designed using the Link and Joint model. We report measured test results from a working Weaver chip in 40 nm CMOS with speeds up to 6 Giga data items per second. With 72 bit wide data items, this amounts to 3.5 Tera bits per second for the full crossbar.

Chapter Contents:

  • 7.1 How fast can a self-timed circuit run?
  • 7.1.1 Logic gate delays
  • 7.1.2 Rings of logic gates
  • 7.1.3 Amplifying pulse signals
  • 7.1.4 The theory of logical effort, or how to make fast circuits
  • 7.1.5 Summary and conclusion of Section 7.1
  • 7.2 The Link and Joint model
  • 7.2.1 Communication versus computation
  • 7.2.2 Initialization and test
  • 7.2.2.1 Action control: go and MrGO
  • 7.2.3 Summary and conclusion of Section 7.2
  • 7.3 The Weaver, an 8 x 8 crossbar experiment
  • 7.3.1 Weaver architecture and floorplan
  • 7.3.1.1 Crossbar switch
  • 7.3.1.2 Steering bits
  • 7.3.1.3 Test infrastructure: scan, counters, and reloaders
  • 7.3.2 Weaver circuits
  • 7.3.2.1 First-in-first-out (FIFO) circuits
  • 7.3.2.2 Critical path: latches to data kiting to double-barrel Links
  • 7.3.2.3 Crossbar circuits: Splitter, Double-barrel Ricochet, Crosser
  • 7.3.3 Test logistics
  • 7.3.3.1 Scan chains and connections to Weaver Links and Joints
  • 7.3.4 How low-speed scan chains test high-speed performance
  • 7.3.5 Performance measurements
  • 7.3.5.1 Throughput versus occupancy at nominal power supply
  • 7.3.5.2 Throughput for various power supply voltages
  • 7.3.5.3 Power for various power supply voltages
  • 7.3.5.4 Power for various data patterns
  • 7.3.6 Summary and conclusion of Section 7.3
  • References

Inspec keywords: integrated circuit design; logic design; CMOS logic circuits; logic testing; integrated circuit testing; asynchronous circuits

Other keywords: complementary metal oxide semiconductor self-timed circuit testing; bit rate 3.5 Tbit/s; flow control; complementary metal oxide semiconductor self-timed circuit design; handshake protocols; asynchronous circuits; size 40 nm; CMOS self-timed circuit design; word length 72 bit; CMOS self-timed circuit testing

Subjects: Digital circuit design, modelling and testing; Logic circuits; Logic and switching circuits; Logic design methods; Semiconductor integrated circuit design, layout, modelling and testing; CMOS integrated circuits

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