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Power-performance balancing of asynchronous circuits

Power-performance balancing of asynchronous circuits

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Asynchronous circuit designed on delay-insensitive NCL and multithreshold CMOS techniques inherits the benefit on power reduction but degrades the speed. Circuit pipeline and parallel architecture are applied to migrate the performance drawback. In the first part of the chapter, the throughput and latency of the NCL micropipeline are derived for the digital signal processing circuit optimization, including an example on generic FIR design with same performance as its synchronous count part. Scalable parallel computing architecture that incorporates homogeneous units is designed in Section 3.2 for performance escalation. Besides that, DVS achieves balanced control of performance and power consumption. An effective fullness variance predicting algorithm is implemented to employ the DVS more aggressively in a wider range of system workloads. The platform fabricated using the MITLL 90 nm process consumes 49.364 pJ per data with the best performance when the DATA to DATA cycle time is 6.02 μ,s. The schemes on fme-grain core states control and heterogeneous architecture are presented as research topics on power -performance balancing. Core enable and disabling sequence and fi ne-grain state control earns the maximum benefit of DVS. Common data I/O ports with NULL cycle reduction and asynchronous arbitration network are incorporated in the heterogeneous platform to make a highly modular interface for both horizontal and vertical scaling. Those methodologies demonstrate the advantage of asynchronous circuit in large scale, multithreads and scalable computing applications.

Chapter Contents:

  • 3.1 Pipelining the asynchronous design
  • 3.1.1 Pipeline balancing
  • 3.1.2 Pipeline dependency
  • 3.2 The parallel architecture and its control scheme
  • 3.2.1 DVS for the homogeneous platform
  • 3.2.2 Pipeline latency and throughput detection
  • 3.2.3 Pipeline fullness and voltage mapping
  • 3.2.4 Workload prediction
  • 3.2.5 Circuit fabrication and measurement
  • 3.3 Advanced topics on power-performance balancing
  • 3.3.1 Homogeneous platform with core disability
  • 3.3.1.1 Core disabling and enabling sequence
  • 3.3.1.2 Fine-grained core state control
  • 3.3.2 Architecture of the heterogeneous platform
  • 3.3.2.1 Multiplexer and demultiplexer design with NULL cycle reduction
  • 3.3.2.2 Asynchronous arbiter design
  • 3.3.2.3 Platform cascading
  • 3.4 Conclusion
  • References

Inspec keywords: logic design; digital signal processing chips; CMOS logic circuits; asynchronous circuits; prediction theory; optimisation

Other keywords: time 6.02 mus; MITLL process; parallel architecture; effective fullness variance predicting algorithm; size 90 nm; delay-insensitive NCL micropipeline; energy 49.364 pJ; scalable parallel computing architecture; NULL cycle reduction; asynchronous circuit design; power-performance balancing; circuit pipeline; digital signal processing circuit optimization; multithreshold CMOS techniques; asynchronous arbitration network; FIR design

Subjects: Logic design methods; Optimisation techniques; Digital signal processing chips; Logic and switching circuits; Digital signal processing chips; CMOS integrated circuits; Optimisation techniques; Logic circuits; Digital circuit design, modelling and testing

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