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Asynchronous circuits for dynamic voltage scaling

Asynchronous circuits for dynamic voltage scaling

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We have presented the appropriateness of the QDI (and pseudo-QDI) asynchronous -logic design approach to realize circuits and systems suitable for full -range DVS (from the nominal voltage near- V t voltage sub- V t voltage regions). Both block -level and gate -level pipeline structures have been presented. Using the block -level pipeline structure, we have presented an SSAVS system embodying block -level QDI asynchronous pipelines for a WSN with the objective of lowest possible power operation for the prevailing throughput and circuit conditions-V DD adjusted to within 50 mV of the minimum voltage, yet high operational robustness with minimal overheads. High robustness has been achieved by adopting the asynchronous QDI protocols, and the embodiment of our proposed PCSL. A reduced -overhead design has further been shown by adopting the asynchronous pseudo-QDI protocols, and the embodiment of PCSL. Using the gate -level pipeline structure, we have presented our proposed SABB cell design approach and evaluated an asynchronous QDI KS pipeline adder embodying SABB for full -range DVS operation. In summary, we show that QDI (and pseudo-QDI) asynchronous -logic, coupled with either PCSL or SABB cell design approaches, provides a low-cost high -reliability solution for circuits and systems exclusively designed for error free DVS.

Chapter Contents:

  • 2.1 Introduction
  • 2.2 Block-level asynchronous circuits
  • 2.2.1 Quasi-delay-insensitive (QDI) sub-threshold self-adaptive VDD scaling (SSAVS)
  • 2.2.1.1 SSAVS system design
  • 2.2.1.2 Precharged-static-logic (PCSL)
  • 2.2.1.3 Block-level QDI asynchronous FRM FB
  • 2.2.1.4 Circuit realization and measurement results
  • 2.2.2 Pseudo-quasi-delay-insensitive sub-threshold self-adaptive VVDD scaling (SSAVS)
  • 2.2.2.1 Asynchronous pseudo-QDI realization approach
  • 2.2.2.2 Timing analysis on the proposed pseudo-QDI realization approach
  • 2.2.2.3 Circuit realization and measurement results
  • 2.3 Gate-level asynchronous circuits
  • 2.3.1 Sense-amplifier half buffer (SAHB)
  • 2.3.2 Design example: Kogge–Stone (KS) 64-bit adder embodying SAHB
  • 2.4 Conclusions
  • References

Inspec keywords: asynchronous circuits; protocols; adders; logic design; circuit reliability; wireless sensor networks; logic gates

Other keywords: asynchronous circuits; SABB cell design approach; SSAVS system; asynchronous-logic design; PCSL; asynchronous pseudoQDI protocols; asynchronous QDI KS pipeline adder; full-range DVS operation; dynamic voltage scaling; block-level pipeline structures; block-level QDI asynchronous pipelines; WSN; reliability; gate-level pipeline structures; voltage 50 mV

Subjects: Reliability; Logic circuits; Digital circuit design, modelling and testing; Logic design methods; Logic and switching circuits; Logic elements

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