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Dual rail asynchronous logic design methodologies for side channel attack mitigation

Dual rail asynchronous logic design methodologies for side channel attack mitigation

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Side channel attacks (SCAs) remain a great threat to hardware security. In most CMOS circuitries, electrical behaviors are correlated to processed data which makes them vulnerable to SCAs. Dual-rail circuitries present an advantage in mitigating SCAs due to the inherited balance in data representation. NCL circuits present more stable power traces compared to industry standard synchronous counterparts; however, NCL circuits are still vulnerable to some SCAs due to the lack of balance in data propagation. In this chapter, the vulnerability of NCL circuits to SCAs is explained, and more secure dual-rail design methodologies are presented. Derived from NCL, dual-spacer dual-rail delay-insensitive logic or D3L methodology produces crypto hardware with great resilience against SCAs. D3L resilience, overheads associated with it as well as improved methodologies for overhead reduction are explained in this chapter.

Chapter Contents:

  • 12.1 Introduction
  • 12.1.1 Side channel attacks
  • 12.1.2 Dual-rail logic solution to SCAs
  • 12.2 NCL SCAs mitigation capabilities and weaknesses
  • 12.2.1 NCL balanced power consumption
  • 12.2.2 NCL unbalanced combinational logic
  • 12.2.3 NCL SCA mitigation
  • 12.3 Dual-spacer dual-rail delay-insensitive logic (D3L)
  • 12.3.1 Introducing an all-ones spacer
  • 12.3.2 Adapting NCL register to the dual-spacer scheme
  • 12.3.2.1 D3L ko generation
  • 12.3.2.2 D3L ki generation
  • 12.3.2.3 D3L filter register
  • 12.3.2.4 D3L spacer generator register
  • 12.3.3 D3L resilience to side channel attacks
  • 12.4 Multi-threshold dual-spacer dual-rail delay-insensitive logic (MTD3L)
  • 12.4.1 The first MTD3L version
  • 12.4.2 Reinvented MTD3L design methodology
  • 12.4.2.1 Approach
  • 12.4.2.2 Spacer generator registers elimination
  • 12.4.2.3 Register cell transistor-level implementation
  • 12.4.2.4 MTD3L simulation and results
  • 12.4.2.5 Side channel attacks resilience
  • 12.5 Results
  • 12.6 Conclusion
  • References

Inspec keywords: CMOS logic circuits; cryptography; logic design; asynchronous circuits

Other keywords: NCL circuits; dual-rail circuitries; D3L methodology; CMOS circuitries; industry standard synchronous counterparts; secure dual-rail design methodologies; overhead reduction; crypto hardware; data propagation; electrical behaviors; side channel attack mitigation; hardware security; dual-spacer dual-rail delay-insensitive logic; dual rail asynchronous logic design methodologies; SCAs; SCA mitigation; data representation

Subjects: CMOS integrated circuits; Logic design methods; Logic and switching circuits; Digital circuit design, modelling and testing; Logic circuits

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