Trojan security aware DSP IP core and integrated circuits

Trojan security aware DSP IP core and integrated circuits

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This chapter discusses different security approaches to designing digital signal processing (DSP) cores that have detection capability against functional-type hardware Trojans in a global supply chain. In the current design and fabrication supply chain, design houses, circuits and system core vendors, and manufacturing houses are globally scattered. It is quite possible that Trojans can be inserted in this design and manufacturing supply chain by anyone involved at any phase. Such Trojans can give backdoors to hackers and affect the operation of the system that uses the infected hardware. In a worst case, in critical applications, such as aircrafts and medical devices, functioning can be completely stopped, causing catastrophic consequences.

Chapter Contents:

  • 3.1 Introduction
  • 3.2 Types of hardware Trojans
  • 3.2.1 Trojan features
  • 3.2.2 Benefit of Trojan security at higher abstraction level
  • 3.2.3 Threat model
  • 3.3 Hardware Trojan in a 3PIP module
  • 3.3.1 Example of a hardware Trojan
  • 3.3.2 Trojan detectability in a 3PIP module at RTL/lower levels
  • 3.4 Selected Trojan security approaches
  • 3.4.1 Trojan security approaches for DSP cores
  • Trojan security approach—Rajendran et al. (2013) and Liu et al. (2014)
  • Trojan security approach—Sengupta et al. (2017a)
  • Trojan security approach—Sengupta et al. (2017b)
  • Trojan security approach—Sengupta et al. (2017c)
  • 3.4.2 Trojan security approach for combinational/sequential circuits
  • 3.5 Trojan security aware DSP IP core
  • 3.5.1 Definition
  • 3.5.2 Goal
  • 3.5.3 Formulation
  • 3.5.4 Models
  • Design area evaluation model
  • Design delay evaluation model
  • Design cost evaluation model
  • 3.6 Design process of Trojan secured DSP IP core
  • 3.6.1 Deriving the CDFG of a DSP core
  • Deriving the CDFG of an 8-point DCT function
  • Deriving the CDFG of an 8-point DFT
  • Deriving the CDFG of the FIR filter
  • 3.6.2 Generating the DMR of the CDFG
  • 3.6.3 Trojan secured scheduling of DMR CDFG
  • Determining resource configuration
  • Vendor allocation procedure
  • 3.7 Analysis of case studies/test cases
  • 3.7.1 DSP applications and system setup for the case studies
  • 3.7.2 Security analysis
  • 3.7.3 Design cost analysis
  • Non-loop CDFG DSP core
  • Single- and nested-loop CDFG DSP cores
  • 3.7.4 Comparative perspectives
  • 3.8 Conclusion
  • 3.9 Exercises
  • References

Inspec keywords: invasive software; integrated circuit manufacture; supply chains; computer crime; digital signal processing chips

Other keywords: hackers; integrated circuits; critical applications; global supply chain; Trojan security; functional-type hardware Trojans; digital signal processing cores; DSP IP core

Subjects: Digital signal processing chips; Digital signal processing chips; Semiconductor integrated circuits

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