As CMOS technology scales down, several challenges have been raised which degrades the performance of the analog charge-pump PLLs. For example, the increasing leakage current of the loop filter capacitor degrades the reference spur, the decreasing output impedance of CMOS device increases the pump -current mismatch, and the severe PVT variations make it almost impossible to have the optimum loop bandwidth over the PVT variations. Note that most of the challenges are caused in the analog loop filter. Therefore, the main motivation of the all -digital PLL (ADPLL) is replacing the analog loop filter to the digital loop filter. In a strict sense, the ADPLL refers to a PLL exclusively built from digital function blocks and does not contain any passive component. In a stricter sense, all components of ADPLL are synthesizable. In general, however, a broad sense of ADPLL defmition is used such that a PLL consists of digital components (especially the digital loop filter) and digital equivalents. In this chapter, the broad sense of ADPLL will be introduced.

Chapter Contents:

• 9.1 Introduction
• 9.2 ADPLL building blocks
• 9.2.1 Digital loop filter
• 9.2.2 Time-to-digital converter
• 9.2.3 Digitally controlled oscillator
• 9.3 Quantization noise and jitter
• 9.3.1 Linearized model of ADPLL
• 9.3.2 Quantization noise of TDC
• 9.3.3 Quantization noise of DCO
• References

Inspec keywords: interference suppression; CMOS digital integrated circuits; digital filters; phase noise; digital phase locked loops

Other keywords: ADPLL; phase noise suppression techniques; digital function blocks; reference spur; analog charge-pump PLLs; digital loop filter; CMOS technology; passive component; CMOS device; loop filter capacitor; pump-current mismatch; all-digital PLL; analog loop filter; digital components

Subjects: Modulators, demodulators, discriminators and mixers; Electromagnetic compatibility and interference; Digital filters; CMOS integrated circuits