Frequency multiplication with a DLL is not as easy as that with a PLL; however, there have been a lot of efforts to adopt DLLs for frequency multiplication, in order to take advantage of its better jitter performance owing to less jitter accumulation. A primitive way is to utilize multiphase clock that can be generated from a type -I DLL [1]. The basic concept is that equally spaced phases at the reference frequency are processed through an edge-combining logic. The simplest example is a frequency doubler shown in Figure 11.1. Basically, we have enough edge information from the original phase (c1k0) and the DLL -generated phase (c1k90), we can produce a doubled frequency. However, any mismatch in the delay elements (i.e., DO 0 D1) or the edge combining logic (i.e., two inputs of the XOR) directly translates into duty -cycle error and deterministic jitter at the output clock. Moreover, programmable multiplication ratio is difficult to achieve.
Phase noise suppression techniques 4: clock multiplying DLL, Page 1 of 2
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