In order to design a big system, it is very important to make a reasonable model of an analog circuit, as it is used to explore how the performance of the analog circuit affects the system performance, without running a time-consuming simulation with physical devices or gates. System Verilog is widely used in those fields for highlevel simulations including analog circuit models. In this appendix, an example of System Verilog modeling of CMOS clock generator is provided. Based on the phase noise and jitter sources of a generic clock generator that we studied in Chapter 6, we include the following jitters in the model: (1) the white (random) jitter induced from the white noise of the output buffer stage, (2) the oscillator phase noise, (3) the phase noise of reference clock, and (4) the sinusoidal jitter. Basically, the purpose of the clock jitter model is to get the phase noise profile from a designer and translate it to the actual timing perturbation.
