One of the primary purposes of reliability evaluation is to identify and protect vulnerable components of a system. At the hardware level, the results of the evaluation can lead to design revisions that aim to increase the fault tolerance of the system. Every potential change is subject to validation and additionally requires more iterations of reliability evaluation. This back-and-forth process is expensive, especially when considering that hardware design changes require significant amounts of time to be applied. To address this problem, microarchitecture-level reliability assessment has been proposed. Instead of assessing the actual hardware design, the evaluation can be performed at microarchitecture-level (or performance) models that are often available very early in the design chain and are both flexible and allow high observability. The existence of reliability evaluation results before the actual design implementation enables early reliability-related design decisions and significantly decreases the cost of redesign cycles. But the absence of transistor-level detail on the evaluation inheritably results to some accuracy loss. Only components that are accurately modeled at the microarchitecture level, which are mostly memory elements (Static Random-Access Memory (SRAM) arrays, flops, and latches), can be assessed. Combinational logic and sequential elements are (in majority) functionally modeled, and thus, they cannot be evaluated at microarchitecture level. Fortunately, literature suggests that only a small portion (< 10%) of failures sources from these elements, which implies that the accuracy loss that can be attributed to the un-modeled resources at microarchitecture-level is limited. In this chapter, we present the throughput, capabilities, and accuracy of microarchitecturelevel reliability assessment, and how it can be effectively used at early design stages.

Chapter Contents:

• 8.1 Introduction
• 8.2 Background
• 8.2.1 Threats and vulnerability
• 8.3 Fault-effect classes
• 8.4 Statistical fault injection
• 8.5 Cross-layer and single-layer evaluation
• 8.6 Assessment throughput
• 8.6.1 Simulation acceleration
• 8.6.1.1 Direct features
• 8.6.1.2 Indirect features
• 8.6.2 Fault list reduction
• 8.7 Estimation accuracy
• 8.8 Conclusions
• References

Inspec keywords: integrated circuit design; microprocessor chips; failure analysis; integrated circuit reliability; flip-flops; sequential circuits; multiprocessing systems; fault tolerance; SRAM chips; combinational circuits

Other keywords: reliability evaluation; redesign cycles; static random-access memory arrays; early reliability-related design decisions; failures sources; microarchitecture-level reliability assessment; combinational logic; transistor-level detail; multicore processors; sequential elements; flops; design revisions; latches; design chain; microarchitecture-level models; fault tolerance; accuracy loss; hardware design; early design stages; SRAM arrays; hardware level; back-and-forth process; memory elements

Subjects: Multiprocessing systems; Logic and switching circuits; Reliability; Microprocessor chips; Microprocessors and microcomputers; Logic circuits; Digital circuit design, modelling and testing