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Soft error modeling and simulation

Soft error modeling and simulation

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Although the sources of soft errors are device-level interactions, the generated errors could propagate and cause system-level failures. As a result, it is very important to analyze the impact of soft errors using a device to system-level approach. Therefore, an efficient soft error vulnerability estimation technique has to be able to accurately model the error generation at device-level as well as the masking behavior at higher abstraction levels. The proposed cross-layer Soft Error Rate (SER) analysis platform employs a combination of empirical models at the device level, error site analysis at chip layout, analytical Error Propagation (EP) at logic level, and fault simulation/emulation at the architecture/application level to provide the detailed contribution of each component (flip-flops, combinational gates, and memory arrays) to the overall SER. At each stage in the modeling hierarchy, an appropriate level of abstraction is used to propagate the effect of errors to the next higher level.

Chapter Contents:

  • 7.1 Introduction
  • 7.2 FIT rate analysis at device level
  • 7.3 Multiple transient error site identification using layout information
  • 7.3.1 Motivation for layout-based MT analysis and mitigation
  • 7.3.2 Proposed layout-based MT error site extraction technique
  • 7.3.2.1 MT error site extraction using MBU analysis
  • 7.3.2.2 Library characterization
  • 7.3.2.3 Overall flow
  • 7.3.3 Experimental results of MT modeling
  • 7.3.3.1 Experimental setup
  • 7.3.3.2 MBU patterns and MT error sites
  • 7.3.3.3 SER estimation
  • 7.3.3.4 Impact of SET/SEU vs. MT model on overall SER
  • 7.3.3.5 Impact of netlist adjacency assumption on SER
  • 7.4 Propagating flip-flop errors at circuit level
  • 7.4.1 Event-driven logic simulation
  • 7.4.2 Error propagation from single flip-flop
  • 7.4.2.1 Error generation at target flip-flop
  • 7.4.2.2 Error propagation through combinational gates in first cycle
  • 7.4.2.3 Error propagation after first cycle
  • 7.4.2.4 Vulnerability time computation
  • 7.4.3 Concurrent transient error propagation from multiple flip-flops
  • 7.4.4 Experimental results
  • 7.4.4.1 Experimental setup
  • 7.4.4.2 Validation of error propagation results
  • 7.4.4.3 Runtime of transient error simulator
  • 7.4.4.4 Independent analysis of masking factors
  • 7.4.4.5 Comparison with other techniques
  • 7.5 Propagating combinational gates errors at circuit level
  • 7.6 Emulation-based fault injection platform
  • 7.6.1 Shadow components
  • 7.6.2 Shadow components-based fault injection technique
  • 7.6.2.1 Fault injection in memory units
  • 7.6.2.2 Fault injection in flip-flops
  • 7.6.3 Experimental results
  • 7.7 Fault injection acceleration
  • 7.7.1 Workflow
  • 7.7.2 Analytical modeling
  • 7.7.3 Case study: fault injection on memory arrays of Leon3
  • 7.7.3.1 Speedup analysis
  • 7.8 Conclusions
  • References

Inspec keywords: estimation theory; fault simulation; combinational circuits; logic gates; flip-flops; radiation hardening (electronics); failure analysis; error analysis

Other keywords: application level; device-level interactions; chip layout; system-level approach; fault emulation; masking behavior; logic level; flip-flops; empirical models; efficient soft error vulnerability estimation technique; system-level failures; memory arrays; abstraction levels; fault simulation; modeling hierarchy; error site analysis; SER analysis platform; analytical error propagation; device level; combinational gates; Soft error modeling; cross-layer soft error rate analysis platform; error generation; architecture level

Subjects: Reliability; Logic circuits; Radiation effects (semiconductor technology); Other topics in statistics; Logic and switching circuits; Other topics in statistics; Logic elements

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